SKP36077 Renesas Electronics America, SKP36077 Datasheet - Page 7

• Manufacturer Part Number: SKP36077
• Description: KIT DEV EVAL FOR H8/36077
• Manufacturer: Renesas Electronics America
• Series: H8®r
• Type: MCUr

Specifications of SKP36077

• Contents: SKP Board, In-Circuit Debugger/Programmer, Target Cable, USB Cable and SKP CD-ROM
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With/related Products: H8/36077
• Lead Free Status / RoHS Status: Supplier Unconfirmed, Lead free / RoHS Compliant

H8 MCUs: Faster
Execution Times
Besides maintaining compat-
ibility within the family,
H8 CPUs have been optimized
for high performance.
The majority of the instruc-
tions in the powerful CISC
instruction set will execute
in one clock cycle, giving
RISC-like operation.
Enhanced Hardware
for Performance
Enhanced
dividers are included in the
CPU core to boost throughput
for mathematical operations
and
performance of the CPU cores.
The H8S/2600 and H8SX
CPU
hardware MAC (Multiply and
Accumulate) block for extra
performance in applications
that involve data computa-
tions.
50
40
30
20
10
further
Dhrystone 1.1 MIPS value
cores
H8S/2000
@ 20 MHz
9 MIPS
multipliers
each
enhance
H8S/2000
have
@ 25 MHz
11 MIPS
and
the
a
H8S/2600
15.2 MIPS
@ 33 MHz
H8 Family CPU Core Overview
Advanced Multiplier
execution cycles
Basic Instructions Execution
Bus Width
No. of Instructions
Address Space
Instruction
MULXU.B
MULXU.W
MULXS.B
MULXS.W
MULU.W
MULU.L
MULS.W
MULS.L
MULU/U.L
MULS/U.L
CLRMAC
LDMAC
STMAC
MAC
@ 35 MHz
35 MIPS
H8SX
H8S
3
4
4
5
1
1
2
4
-
-
-
-
-
-
@ 50 MHz
50 MIPS
H8SX
H8SX
2 cycles
H8/300
1
1
2
2
2
5
2
5
6
6
1
1
1
4
64KB
8-bit
57
H8/300H
2 cycles
16MB
16-bit
64
Advanced Divider
execution cycles
H8 MCU System
Performance
H8 microcontrollers are designed to
deliver high throughput for excellent
application performance.
For example, their CISC CPU cores
execute most instructions in just one
clock cycle, and their Advanced
Data
utilize a 3-bus architecture to speed
data transfers.
Also, the on-chip Flash can be
accessed in a single cycle, achieving
the
per MHz.
Instruction
DIVXU.B
DIVU.W
DIVXU.W
DIVU.L
DIVXS.B
DIVS.W
DIVXS.W
DIVS.L
The H8 Architecture
best
H8S/2000
1 cycle
16-bit
16MB
Management
65
possible
H8S
12
20
13
21
-
-
-
-
H8S/2600
1 cycle
16-bit
16MB
69
performance
peripherals
H8SX
10
10
18
18
12
11
20
19
1 cycle
H8SX
32-bit
4GB
87