AT91CAP9A-STK Atmel, AT91CAP9A-STK Datasheet - Page 54

• Manufacturer Part Number: AT91CAP9A-STK
• Description: KIT STARTER FOR AT91CAP9A
• Manufacturer: Atmel
• Series: CAP™r
• Type: MCUr

Specifications of AT91CAP9A-STK

• Contents: Board, CD
• For Use With/related Products: AT91CAP9
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

D
C
B
A
Fast AS (40 MHz)
Remote system upgrade fast AS (40 MHz)
AS (20 MHz)
Remote system upgrade AS (20 MHz)
3V3
CONFIGURATION SCHEME
C292
C292
1UF_16V
1UF_16V
EPCS16SI16N
EPCS16SI16N
U20
U20
11
12
13
14
3
4
5
6
C276
C276
10nF
10nF
DCLK
CONF_DONE
nCONFIG
DATA0
ASDO_FPGA
NC3
NC4
NC5
NC6
NC11
NC12
NC13
NC14
W EAK PULLUP ENABLED
3V3
5
C277
C277
10nF
10nF
DATA
DCLK
ASDI
CS
nIO_PULLUP
HE10_MD_2X5
HE10_MD_2X5
1
3
5
7
9
CONF_DONE
8
16
7
15
MSEL3
1
3
5
7
9
C278
C278
10nF
10nF
J65
J65
1
1
1
1
10
2
4
6
8
DATA0
DCLK
nCSO
ASDO_FPGA
VCCIO7
2
4
6
8
10
MSEL2
R193
R193
10K
10K
NC
NC
R196
R196
1K
1K
0
0
1
1
3V3
MSEL1
0
0
0
1
nCE
nCSO
nCE
nCSO
DCLK
ASDO_FPGA
3V3
R194
R194
10K
10K
NC
NC
MSEL0
0
1
1
0
TP49
TP49
TP51
TP51
R216
R216
0R
0R
R217
R217
0R
0R
R218
R218
0R
0R
R219
R219
0R
0R
R195
R195
10K
10K
TP50
TP50
TP56
TP56
TP57
TP57
R201
R201
1K
1K
nIO_PULLUP
NC
NC
NC
NC
NC
NC
NC
NC
nCE
AS MODE CONFIGURATION
R202
R202
1K
1K
MSEL3
MSEL2
MSEL1
MSEL0
W11
4
D11
G12
E12
V12
E13
H12
D17
A19
E16
E17
B19
D18
AB2
AA3
B20
A21
D19
C20
V5
C3
A2
nCE_CAP9
nCSO_CAP9
DCLK_CAP9
ASDO_CAP9
EP2S15F484
EP2S15F484
EP2S15F484
EP2S15F484
U19J
U19J
nCSO
ASDO
CRC_ERROR
DEV_CLRn
DEV_OE
DATA0
DATA1
DATA2
DATA3
DATA4
DATA5
DATA6
DATA7
U19I
U19I
nIO_PULLUP
nCEO
PORSEL
TEMPDIODEn
TEMPDIODEp
nSTATUS
nCE
DCLK
CONF_DONE
VCCIO4
R206
R206
10K
10K
NC
NC
R210
R210
1K
1K
CONFIGURATION/JTAG
CONFIGURATION/JTAG
R207
R207
10K
10K
NC
NC
R211
R211
1K
1K
INIT_DONE
RDYnBSY
nCONFIG
FPGA Clock & Configuration
OPTIONS
OPTIONS
CLKUSR
VCCSEL
RUnLU
MSEL3
MSEL2
MSEL1
MSEL0
PGM0
PGM1
PGM2
TRST
nWS
TDO
TMS
nCS
nRS
TCK
TDI
R208
R208
10K
10K
NC
NC
R213
R213
1K
1K
CS
E18
W12
T16
W17
V16
U16
F17
H11
E11
D12
V11
A4
B4
D4
E5
B3
AB21
AA20
AA19
AB19
W18
V17
R209
R209
10K
10K
R214
R214
1K
1K
NC
NC
R203
R203
1K
1K
MSEL3
MSEL2
MSEL1
MSEL0
TDO
TDI
TMS
TCK
TRST
nCONFIG
TP52
TP52
TP53
TP53
TP54
TP54
R200
R200
10K
10K
NC
NC
VCCIO8
R191
R191
10K
10K
NC
NC
R192
R192
1K
1K
NC
NC
VCCIO7
J69
J69
3
R199
R199
10K
10K
3V3
TP55
TP55
3V3
R212
R212
0R
0R
R198
R198
0R
0R
TMS_ICE
TCK_ICE
TDO_FPGA
TDO_CAP9
R221
R221
0R
0R
MPIOB24
R215
R215
1K
1K
NC
NC
FPGA_PLL5OUTp
FPGA_PLL5FBp
MPIOB24
RESET_FPGA#
C288
C288
10pF
10pF
NTRST
1
1
1
1
Rév.
Rév.
Rév.
C02 21/05/08
C02 21/05/08
C02 21/05/08
J61
J61
1X3PTS_MD_2MM54
1X3PTS_MD_2MM54
J62
J62
1X3PTS_MD_2MM54
1X3PTS_MD_2MM54
J63
J63
1X3PTS_MD_2MM54
1X3PTS_MD_2MM54
J64
J64
1X3PTS_MD_2MM54
1X3PTS_MD_2MM54
Date
Date
Date
M21
N20
M20
N19
N22
N21
C10
D10
L21
L20
A10
B10
N3
M2
N4
M3
N1
N2
Y4
B9
C9
L2
L3
3
3
3
3
Auteur
Auteur
Auteur
OBO
OBO
OBO
EP2S15F484
EP2S15F484
U19K
U19K
CLK1p
CLK3p
CLK9p
CLK11p
CLK1n
CLK3n
CLK9n
CLK11n
CLK0p/DIFFIO_RX_C0p
CLK2p/DIFFIO_RX_C1p
CLK8p/DIFFIO_RX_C2p
CLK10p/DIFFIO_RX_C3p
CLK0n/DIFFIO_RX_C0n
CLK2n/DIFFIO_RX_C1n
CLK8n/DIFFIO_RX_C2n
CLK10n/DIFFIO_RX_C3n
PLL_ENA
PLL5_OUT0p
PLL5_OUT1p
PLL5_OUT0n
PLL5_OUT1n
PLL5_FBp/OUT2p
PLL5_FBn/OUT2n
Création
Création
Création
2, Chemin du Ruisseau BP 121
2, Chemin du Ruisseau BP 121
2, Chemin du Ruisseau BP 121
69136 Ecully
69136 Ecully
69136 Ecully
Tél : [phone]
Tél : [phone]
Tél : [phone]
Fax : [phone]
Fax : [phone]
Fax : [phone]
www.adeneo.adetelgroup.com
www.adeneo.adetelgroup.com
www.adeneo.adetelgroup.com
Historique / Background history
Historique / Background history
Historique / Background history
2
TMS_BYTEB
TMS
TCK_BYTEB
TCK
TDO_BYTEB
TDO
TDI_FPGA
TDI
1
2
K3750HBE-12MHz
K3750HBE-12MHz
OE
GND
Y5
Y5
R197
R197
10K
10K
PLL6_FBp/OUT2p
PLL6_FBn/OUT2n
VCC
OUT
CLOCK & PLL
CLOCK & PLL
PLL6_OUT0p
PLL6_OUT1p
PLL6_OUT0n
PLL6_OUT1n
CLK12p
CLK13p
CLK14p
CLK15p
CLK12n
CLK13n
CLK14n
CLK15n
4
3
CLK4p
CLK5p
CLK6p
CLK7p
CLK4n
CLK5n
CLK6n
CLK7n
Format
Format
Format
A3
A3
A3
Projet / Project
Projet / Project
Projet / Project
Schéma électronique / Schematic
Schéma électronique / Schematic
Schéma électronique / Schematic
Date:
Date:
Date:
CLK_12M_R
CAP9-STK
CAP9-STK
CAP9-STK
FPGA CLOCK & CONFIG
FPGA CLOCK & CONFIG
FPGA CLOCK & CONFIG
R150
R150
1K
1K
TCK_BYTEB
TDO_BYTEB
TMS_BYTEB
TDI_FPGA
AB13
AA12
AA11
Y10
B11
B12
A13
C13
AA13
Y12
Y11
W10
C11
C12
B13
D13
AB10
AA9
AA10
Y9
W9
V9
Dessinateur / Drawer
Dessinateur / Drawer
Dessinateur / Drawer
O. Boitet
O. Boitet
O. Boitet
Tuesday, May 20, 2008
Tuesday, May 20, 2008
Tuesday, May 20, 2008
C279
C279
330pF
330pF
R204
R204
22R
22R
FPGA_PLL6OUTp
FPGA_PLL6FBp
JTAG
HE10_MD_2X5
HE10_MD_2X5
1
3
5
7
9
CLK_12M_FPGA
1
3
5
7
9
1
C280
C280
100nF
100nF
J57
J57
BLM18PG600
BLM18PG600
10
2
4
6
8
R220
R220
0R
0R
2
4
6
8
10
L25
L25
Référence / Reference
Référence / Reference
Référence / Reference
ADEC101389001
ADEC101389001
ADEC101389001
2
1
Page
Page
Page
3V3
3V3
C281
C281
100nF
100nF
13
13
13
de / of
de / of
de / of
21
21
21
C02
C02
C02
Rév.
Rév.
Rév.
D
C
B
A