AT91CAP9A-STK Atmel, AT91CAP9A-STK Datasheet - Page 34

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AT91CAP9A-STK

Manufacturer Part Number
AT91CAP9A-STK
Description
KIT STARTER FOR AT91CAP9A
Manufacturer
Atmel
Series
CAP™r
Type
MCUr
Datasheets

Specifications of AT91CAP9A-STK

Contents
Board, CD
For Use With/related Products
AT91CAP9
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
2.4.1.14 F14: Programming and Configuration
2.4.1.14.1JTAG Programming
Table 2-20. Jumper Position Configuration
2.4.1.14.2Serial Device Configuration
AT91CAP9-STK Starter Kit User Guide
Programming
ICE-only JTAG
JTAG chains
Stand-alone
daisy chain
Chain
JTAG
J59 Jumper
Two jumpers on the 3-pin connectors, J16 and J17 define reset configuration of the board and the way
status reset signals are driven.
Status reset signals are:
Table 2-19. Reset Configuration
Two different JTAG programming chains are implemented on the board:
Each programmable device (microcontroller and FPGA) has it's own JTAG programming chain.
“EI11: JTAG and Serial Configuration Interfaces” on page
It's possible to use only the ICE-JTAG interface to program microcontroller and FPGA on a unique JTAG
daisy chain. AT91CAP9 is the first device in the daisy chain, FPGA is the second one.
Configuration of the jumper positions must be as shown in the table that follows.
Three ways can be used to program the FPGA EPCS16 serial device.
The FPGA EPCS16 serial device configuration can be programmed via the EI11 serial device configura-
tion port with Altera USB Blaster probe.
Position
Configuration
DONE_FPGA: the CONF_DONE FPGA configuration status signal
DONE_FPGA_CAP9: indicates the FPGA configuration status to the AT91CAP9 microcontroller (PIO
Stand-alone JTAG chains (default)
ICE-only JTAG daisy chain
Serial device configuration port
Altera SFL (Serial Flash Loader) function
1-2
2-3
– ICE-JTAG chain for AT91CAP9 JTAG programming
– USB-Blaster chain for FPGA JTAG programming
Reset
1
2
3
4
J60 Jumper
Position
Reset CAP9 resets FPGA, start CAP9 and then start FPGA
Reset FPGA resets CAP9, start FPGA and then start CAP9
2-3
1-2
Uncontrolled reset-then-start CAP9 and FPGA order
J61 Jumper
Forbidden (no reset available)
Position
2-3
1-2
Reset Description
J62 Jumper
Position
2-3
1-2
2-7.)
J63 Jumper
Position
2-3
1-2
J16 Jumper
J64 Jumper
Position
Position
1-2
1-2
2-3
2-3
2-3
1-2
6351B–CAP–27-Jun-08
Requirements
Default chain
J17 Jumper
Position
Note
1-2
2-3
1-2
2-3
-
(See
2-27

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