ATEVK1104S Atmel, ATEVK1104S Datasheet - Page 84

• Manufacturer Part Number: ATEVK1104S
• Description: KIT EVAL FOR AT32UC
• Manufacturer: Atmel
• Series: AVR®32 UC3r
• Type: MCUr

Specifications of ATEVK1104S

• Contents: Board, Cables
• Tool Type: Development Kit
• Cpu Core: AVR 32
• Data Bus Width: 32 bit
• Processor Series: AT32
• Processor To Be Evaluated: AT32UC3A3256S
• Interface Type: USB, JTAG, SD Card, Nexus, MMC
• Core Architecture: AVR
• Operating Supply Voltage: 5.5 V
• For Use With/related Products: *
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

13.2.7
13.2.8
13.2.9
13.2.10
32072C–AVR32–2010/03
PDCA
AES
HMATRIX
TWIM
3. USART in ISO7816 mode Only in T1: RX impossible after any TX
1. PCONTROL.CHxRES is nonfunctional
2. Transfer error will stall a transmit peripheral handshake interface.
1. URAD (Unspecified Register Access Detection Status) does not detect read accesses
1. In the HMATRIX PRAS and PRBS registers MxPR fields are only two bits
1. TWIM SR.IDLE goes high immediately when NAK is received
USART Control Register (CR). This will drive the RTS output high. After the next DMA trans-
fer is started and a receive buffer is available, write a one to the RTSEN bit in the USART
CR so that RTS will be driven low.
Fix/workaround
Reset the TX transceiver by setting RSTTX field in CR register, then configure MR register
and CR register.
PCONTROL.CHxRES is nonfunctional. Counters are reset at power-on, and cannot be
reset by software.
Fix/Workaround
Software needs to keep history of performance counters.
If a tranfer error is encountered on a channel transmitting to a peripheral, the peripheral
handshake of the active channel will stall and the PDCA will not do any more transfers on
the affected peripheral handshake interface.
Fix/workaround:
Disable and then enable the peripheral after the transfer error.
to the write-only KEYW[5..8]R registers
Fix/Workaround
None.
In the HMATRIX PRAS and PRBS registers MxPR fields are only two bits wide, instead of
four bits. The unused bits are undefined when reading the registers.
Fix/Workaround
Mask undefined bits when reading PRAS and PRBS.
When a NAK is received and there is a non-zero number of bytes to be transmitted,
SR.IDLE goes high immediately and does not wait for the STOP condition to be sent. This
does not cause any problem just by itself, but can cause a problem if software waits for
SR.IDLE to go high and then immediately disables the TWIM by writing a one to CR.MDIS.
Disabling the TWIM causes the TWCK and TWD pins to go high immediately, so the STOP
condition will not be transmitted correctly.
Fix/Workaround
If possible, do not disable the TWIM. If it is absolutely necessary to disable the TWIM, there
must be a software delay of at least two TWCK periods between the detection of
SR.IDLE==1 and the disabling of the TWIM.
AT32UC3A3/A4
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