ATEVK1104S Atmel, ATEVK1104S Datasheet - Page 5

• Manufacturer Part Number: ATEVK1104S
• Description: KIT EVAL FOR AT32UC
• Manufacturer: Atmel
• Series: AVR®32 UC3r
• Type: MCUr

Specifications of ATEVK1104S

• Contents: Board, Cables
• Tool Type: Development Kit
• Cpu Core: AVR 32
• Data Bus Width: 32 bit
• Processor Series: AT32
• Processor To Be Evaluated: AT32UC3A3256S
• Interface Type: USB, JTAG, SD Card, Nexus, MMC
• Core Architecture: AVR
• Operating Supply Voltage: 5.5 V
• For Use With/related Products: *
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

2.1
2.1.1
2.1.2
2.1.3
2.1.4
32072C–AVR32–2010/03
Processor and Architecture
AVR32 UC CPU
Debug and Test System
Peripheral DMA Controller
Bus System
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32-bit load/store AVR32A RISC architecture
Three stage pipeline allows one instruction per clock cycle for most instructions
MPU allows for operating systems with memory protection
IEEE1149.1 compliant JTAG and boundary scan
Direct memory access and programming capabilities through JTAG interface
Extensive On-Chip Debug features in compliance with IEEE-ISTO 5001-2003 (Nexus 2.0) Class 2+
Auxiliary port for high-speed trace information
Hardware support for six Program and two data breakpoints
Unlimited number of software breakpoints supported
Advanced Program, Data, Ownership and Watchpoint trace supported
Transfers from/to peripheral to/from any memory space without intervention of the processor
Next Pointer Support, forbids strong real-time constraints on buffer management
Eight channels and 24 Handshake interfaces
High Speed Bus (HSB) matrix with 7 Masters and 10 Slaves handled
Peripheral Bus A able to run on at divided bus speeds compared to the High Speed Bus
– 15 general-purpose 32-bit registers
– 32-bit Stack Pointer, Program Counter and Link Register reside in register file
– Fully orthogonal instruction set
– Privileged and unprivileged modes enabling efficient and secure Operating Systems
– Innovative instruction set together with variable instruction length ensuring industry leading
– DSP extension with saturating arithmetic, and a wide variety of multiply instructions
– Byte, halfword, word and double word memory access
– Multiple interrupt priority levels
– Low-cost NanoTrace supported
– Two for each USART
– Two for each Serial Synchronous Controller (SSC)
– Two for each Serial Peripheral Interface (SPI)
– One for ADC
– Four for each TWI Interface
– Two for each Audio Bit Stream DAC
– Handles Requests from
– Round-Robin Arbitration (three modes supported: no default master, last
– Burst breaking with Slot Cycle Limit
– One address decoder provided per master
code density
master, fixed default master)
• Masters: the CPU (Instruction and Data Fetch), PDCA, CPU SAB, USBB, DMACA
• Slaves: the internal Flash, internal SRAM, Peripheral Bus A, Peripheral Bus B, External
Bus Interface (EBI), Advanced Encrytion Standard (AES)
AT32UC3A3/A4
accessed default
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