ATSAM3S-EK Atmel, ATSAM3S-EK Datasheet - Page 37
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ATSAM3S-EK
Manufacturer Part Number
ATSAM3S-EK
Description
KIT EVAL FOR ATSAM3S4C
Manufacturer
Atmel
Series
SAM3Sr
Type
MCUr
Specifications of ATSAM3S-EK
Contents
Board, Cables, Power Supply
Silicon Manufacturer
Atmel
Core Architecture
ARM
Core Sub-architecture
Cortex-M3
Kit Contents
Board
Features
TFT Colour LCD Display, SD/MMC Interface
Svhc
No SVHC (15-Dec-2010)
Rohs Compliant
Yes
For Use With/related Products
*
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
ATSAM3S-EK
Manufacturer:
Atmel
Quantity:
135
10.5
6500CS–ATARM–24-Jan-11
Clock Generator
The reset circuitry is based on a zero-power power-on reset cell and a brownout detector cell.
The zero-power power-on reset allows the Supply Controller to start properly, while the soft-
ware-programmable brownout detector allows detection of either a battery discharge or main
voltage loss.
The Slow Clock generator is based on a 32 kHz crystal oscillator and an embedded 32 kHz RC
oscillator. The Slow Clock defaults to the RC oscillator, but the software can enable the crystal
oscillator and select it as the Slow Clock source.
The Supply Controller starts up the device by sequentially enabling the internal power switches
and the Voltage Regulator, then it generates the proper reset signals to the core power supply.
It also enables to set the system in different low power modes and to wake it up from a wide
range of events.
The Clock Generator is made up of:
• One Low Power 32768Hz Slow Clock oscillator with bypass mode
• One Low-Power RC oscillator
• One 3-20 MHz Crystal Oscillator, which can be bypassed
• One Fast RC oscillator factory programmed, 3 output frequencies can be selected: 4, 8 or 12
• One 60 to 130 MHz PLL (PLLB) providing a clock for the USB Full Speed Controller
• One 60 to 130 MHz programmable PLL (PLLA), capable to provide the clock MCK to the
MHz. By default 4 MHz is selected.
processor and to the peripherals. The PLLA input frequency is from 3.5 to 20 MHz.
SAM3S Summary
37