DK-DEV-3CLS200N Altera, DK-DEV-3CLS200N Datasheet - Page 38
DK-DEV-3CLS200N
Manufacturer Part Number
DK-DEV-3CLS200N
Description
KIT DEV CYCLONE III LS EP3CLS200
Manufacturer
Altera
Series
Cyclone® IIIr
Type
FPGAr
Datasheets
1.EP3C5F256C8N.pdf
(34 pages)
2.EP3C5F256C8N.pdf
(14 pages)
3.DK-START-3C25N.pdf
(74 pages)
4.DK-DEV-3CLS200N.pdf
(42 pages)
Specifications of DK-DEV-3CLS200N
Contents
Board
Silicon Manufacturer
Altera
Core Architecture
FPGA
Core Sub-architecture
Cyclone
Silicon Core Number
EP3C
Silicon Family Name
Cyclone III LS
Rohs Compliant
Yes
For Use With/related Products
EP3CLS200
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Other names
544-2601
1
2
MAX II CPLD Features
Devices
An external resistor must be used for a 5-V tolerance.
36
Typical equivalent macrocells.
Altera Product Catalog
Equivalent macrocells
Pin-to-pin delay (ns)
User flash memory (Kb)
Boundary scan JTAG
JTAG ISP
Fast input registers
Programmable register
power up
JTAG translator
Real-time ISP
MultiVolt I/Os (V)
I/O power banks
Maximum output enables
LVTTL/LVCMOS
32-bit, 66-MHz PCI compliant
Schmitt triggers
Programmable slew rate
Programmable pull-up resistors
Programmable ground pins
Open-drain outputs
Bus hold
•
1
2011
•
www.altera.com
1.5, 1.8, 2.5, 3.3
EPM240/Z
4.7, 7.5
192
80
2
-
1.5, 1.8, 2.5, 3.3
EPM570/Z
MAX II CPLDs (3.3 V, 2.5 V, 1.8 V)
5.4, 9.0
440
160
2
-
3
3
3
3
3
3
3
3
3
3
3
3
3
8
1.5, 1.8, 2.5, 3.3, 5.0
EPM1270
980
212
6.2
3
4
2
2
1.5, 1.8, 2.5, 3.3, 5.0
EPM2210
1,700
272
7.0
3
4
2
2