DK-DEV-3CLS200N Altera, DK-DEV-3CLS200N Datasheet - Page 29

• Manufacturer Part Number: DK-DEV-3CLS200N
• Description: KIT DEV CYCLONE III LS EP3CLS200
• Manufacturer: Altera
• Series: Cyclone® IIIr
• Type: FPGAr

Specifications of DK-DEV-3CLS200N

• Contents: Board
• Silicon Manufacturer: Altera
• Core Architecture: FPGA
• Core Sub-architecture: Cyclone
• Silicon Core Number: EP3C
• Silicon Family Name: Cyclone III LS
• Rohs Compliant: Yes
• For Use With/related Products: EP3CLS200
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 544-2601

LEs
M10K memory blocks (Kb)
MLAB
PLLs
Global clock networks
DSP blocks
PCIe hard IP blocks
Memory controllers
I/O voltage levels supported (V)
I/O standards supported
LVDS channels (875 Mbps receive,
840 Mbps transmit)
Transceiver (SERDES) channels
Memory devices supported
LVTTL, LVCMOS, PCI, PCI-X, LVDS, mini-LVDS, RSDS, LVPECL, Differential SSTL-15, Differential SSTL-18,
Differential SSTL-2, Differential HSTL-12, Differential HSTL-15, Differential HSTL-18, SSTL-15 (I and II),
5CGTD3
75,000
4,620
SSTL-18 (I and II), SSTL-2 (I and II), 1.2-V HSTL (I and II), 1.5-V HSTL (I and II),
132
100
16
6
2
6
2
Cyclone V GT FPGAs (1.1 V), 5G Transceivers
1.8-V HSTL (I and II), HiSpi, SLVS, Sub-LVDS
25% of ALMs can be configured as MLABs
DDR3, DDR2, DDR, LPDDR, LPDDR2
1.1, 1.2, 1.5, 1.8, 2.5, 3.3
5CGTD5
150,000
Altera Product Catalog
6,160
220
122
16
7
2
2
9
Cyclone V GT FPGA Features
•
2011
•
www.altera.com
5CGTD8
300,000
12,760
406
122
16
12
8
2
2
Devices
27