BMSKTOPASA900(DCE) Toshiba, BMSKTOPASA900(DCE) Datasheet - Page 3

KIT STARTER TMPA900 USB JTAG

BMSKTOPASA900(DCE)

Manufacturer Part Number
BMSKTOPASA900(DCE)
Description
KIT STARTER TMPA900 USB JTAG
Manufacturer
Toshiba
Series
TOPASr
Type
MCUr
Datasheets

Specifications of BMSKTOPASA900(DCE)

Contents
Evaluation Board, Cable(s), Software and Documentation
For Use With/related Products
TMPA900CMXBG
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
OFD is the required H/W implementation to comply with the „
safety of Electrical Equipment
erates a Reset when the high oscillation frequency (f
the normal frequency range specified by the lower and higher detection
frequency setting registers.
An abnormal frequency condition can be detected via the external OFD
The high-frequency clock (f
frequency clock (f
reference clock stops due to an external cause, the OFD detects an abnormal
condition and resets the internal circuitry as well.
A 7-Layer multi bus system has been implemented in
order to increase the overall performance drastically.
Even MPEG4 or H.264 videos can be handled while
scaling is supported by the LCD accelerator.
Following bus masters can operate individually:
Overview Toshiba ARM Display Microcontroller
Oscillation Frequency Detector (OFD)
Multi-Layer Bus System
Bus Master 1:
Bus Master 2:
Bus Master 3:
Bus Master 4:
Bus Master 5:
Bus Master 6:
Bus Master 7:
s
: 32KHz) is used as a reference clock. If the 32 KHz
CPU data
CPU instruction
LCD controller
LCD data process accelerator
DMA controller 1
DMA controller 2
USB device controller
OSC
“ in accordance with IEC60730 (Class B). It gen-
) is used as a detection clock, and the low-
OSC
) falls or rises outside of
- 3 -
Standard for
OUTn
pin.
ARM9 Microcontroller
TMPA900CMXBG

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