C8051F005DK Silicon Laboratories Inc, C8051F005DK Datasheet - Page 159
C8051F005DK
Manufacturer Part Number
C8051F005DK
Description
DEV KIT FOR F005/006/007
Manufacturer
Silicon Laboratories Inc
Type
MCUr
Datasheet
1.C8051F005-TB.pdf
(171 pages)
Specifications of C8051F005DK
Contents
Evaluation Board, Power Supply, USB Cables, Adapter and Documentation
Processor To Be Evaluated
C8051F01x
Interface Type
USB
Silicon Manufacturer
Silicon Labs
Core Architecture
8051
Silicon Core Number
C8051F005
Silicon Family Name
C8051F00x
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
For Use With/related Products
Silicon Laboratories C8051 F005/006/007
Lead Free Status / Rohs Status
Lead free / RoHS Compliant
Other names
336-1188
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
C8051F005DK
Manufacturer:
SiliconL
Quantity:
1
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20.2.
The 16-bit PCA counter/timer consists of two 8-bit SFRs: PCA0L and PCA0H. PCA0H is the high byte (MSB) of
the 16-bit counter/timer and PCA0L is the low byte (LSB).
PCA0H at the same time. By reading the PCA0L Register first, this allows the PCA0H value to be held (at the time
PCA0L was read) until the user reads the PCA0H Register. Reading PCA0H or PCA0L does not disturb the
counter operation. The CPS1 and CPS0 bits in the PCA0MD register select the timebase for the counter/timer as
shown in Table 20.2.
When the counter/timer overflows from 0xFFFF to 0x0000, the Counter Overflow Flag (CF) in PCA0MD is set to
logic 1 and an interrupt request is generated if CF interrupts are enabled. Setting the ECF bit in PCA0MD to logic 1
enables the CF flag to generate an interrupt request. The CF bit is not automatically cleared by hardware when the
CPU vectors to the interrupt service routine, and must be cleared by software. (Note: PCA0 interrupts must be
globally enabled before CF interrupts are recognized. PCA0 interrupts are globally enabled by setting the EA bit
(IE.7) and the EPCA0 bit in EIE1 to logic 1.) Clearing the CIDL bit in the PCA0MD register allows the PCA to
continue normal operation while the microcontroller core is in Idle mode.
159
C8051F000/1/2/5/6/7
C8051F010/1/2/5/6/7
SYSCLK/12
SYSCLK/4
Timer 0 Overflow
ECI
PCA Counter/Timer
CPS1
C
D
L
I
0
0
1
1
PCA0MD
00
01
10
11
C
P
S
1
C
CPS0
P
S
0
E
C
F
0
1
0
1
Figure 20.7. PCA Counter/Timer Block Diagram
IDLE
Table 20.2. PCA Timebase Input Options
C
F
Timebase
System clock divided by 12
System clock divided by 4
Timer 0 overflow
High-to-low transitions on ECI (max rate = system clock divided by 4)
C
R
PCA0CN
C
C
F
4
C
C
F
3
C
C
F
2
C
C
F
1
C
C
F
0
Rev. 1.7
0
1
PCA0L
read or
write
Snapshot
Register
PCA0H
Reading PCA0L automatically latches the value of
PCA0L
To SFR Bus
To PCA Modules
Overflow
CF
To PCA Interrupt System
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