XE8000EV101 Semtech, XE8000EV101 Datasheet - Page 66

• Manufacturer Part Number: XE8000EV101
• Description: EVAL BOARD FOR XE8801AMI027LF
• Manufacturer: Semtech
• Type: MCUr

Specifications of XE8000EV101

• Contents: Fully Assembled Evaluation Board
• For Use With/related Products: XE88LC01AMI027
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant

Note: Depending on the status of the EnResPConf bit in RegSysCtrl, the reset conditions of the registers are
different. See the reset block documentation for more details on the resetpconf signal.
12.4 Port B capabilities
Table 12-7 shows the different usage that can be made of Port B with the order of priority. If a pair of pins is
selected to be analog, it overwrites the function and digital set-up. If the pin is not selected as analog, but a
function is enabled, it overwrites the digital set-up. If neither the analog nor function are selected for a pin, it is used
as an ordinary digital I/O. This is the default configuration at start-up.
12.5 Port B analog capability
12.5.1
Port B terminals can be attached to a 4 line analog bus by setting the PBAna[x] bits to 1 in the RegPBAna
register.
The other registers then define the connection of these 4 analog lines to the different pads of Port B. This can be
used to implement a simple LCD driver or A/D converter. Analog switching is available only when the circuit is
powered with sufficient voltage (see specification below). Below the specified supply voltage, only voltages that are
close to VSS or VBAT can be switched.
When PBAna[x] is set to 1, a pair of Port B terminals is switched from digital I/O mode to analog mode. The usage
of the registers RegPBPullup, RegPBOut and RegPBDir define the analog configuration (see Table 12-8).
When PBAna[x] = 1, then PBPullup[x] connects the pin to the analog bus. PBDir[x] and PBPOut[x] select which
of the 4 analog lines is used. For odd values of x, the selection bits are in the register RegPBOut (see Table 12-8).
For even values of x, the selection bits are in the register RegPBDir (see Table 12-9).
© Semtech 2005
Pos.
7 – 4
3
2
1
0
--
PBAna [3]
PBAna [2]
PBAna [1]
PBAna [0]
Port B analog configuration
RegPBAna
Port B
name
PB[7]
PB[6]
PB[5]
PB[4]
PB[3]
PB[2]
PB[1]
PB[0]
r
r w
r w
r w
r w
rw
analog
analog
analog
analog
analog
(high)
0000
0 resetpconf
0 resetpconf
0 resetpconf
0 resetpconf
Table 12-7: Different Port B functionality
reset
PWM1 Counter C (C+D)
PWM0 Counter A (A+B)
Table 12-6: RegPBAna
Unused
Set PB[7:6] in analog mode
Set PB[5:4] in analog mode
Set PB[3:2] in analog mode
Set PB[1:0] in analog mode
description in digital mode
clock CPU
functions
(medium)
uart Rx
usrt S1
usrt S0
32 kHz
uart Tx
usage (priority)
12-3
(low) (default)
Unused
Set PB[7:6] in analog mode
Set PB[5:4] in analog mode
Set PB[3:2] in analog mode
Set PB[1:0] in analog mode
digital
description in analog mode
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
XE8801A – SX8801R
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