EVAL-ADUC831QSZ Analog Devices Inc, EVAL-ADUC831QSZ Datasheet - Page 29

• Manufacturer Part Number: EVAL-ADUC831QSZ
• Description: KIT DEV FOR ADUC831 QUICK START
• Manufacturer: Analog Devices Inc
• Series: QuickStart™ Kitr
• Type: MCUr

Specifications of EVAL-ADUC831QSZ

• Contents: Evaluation Board, Power Supply, Cable, Software and Documentation
• Silicon Manufacturer: Analog Devices
• Core Architecture: 8051
• Silicon Core Number: ADuC831
• Tool / Board Applications: General Purpose MCU, MPU, DSP, DSC
• Mcu Supported Families: ADUC8xx
• Development Tool Type: Hardware - Eval/Demo Board
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With/related Products: ADuC831
• Lead Free Status / Rohs Status: Compliant
• Other names: EVAL-ADUC831QS; EVAL-ADUC831QS

USING THE FLASH/EE DATA MEMORY
The 4 kBytes of Flash/EE data memory is configured as 1024
pages, each of four bytes. As with the other ADuC831 peripherals,
the interface to this memory space is via a group of registers mapped
in the SFR space. A group of four data registers (EDATA1–4)
are used to hold the four bytes of data at each page. The page is
addressed via the two registers EADRH and EADRL. Finally,
ECON is an 8-bit control register that may be written with one
of nine Flash/EE memory access commands to trigger various
read, write, erase, and verify functions.
A block diagram of the SFR interface to the Flash/EE data
memory array is shown in Figure 20.
ECON—Flash/EE Memory Control SFR
Programming of either the Flash/EE data memory or the Flash/EE
program memory is done through the Flash/EE memory control
SFR (ECON). This SFR allows the user to read, write, erase, or
verify the 4 kBytes of Flash/EE data memory or the 56 kBytes of
Flash/EE program memory.
ECON VALUE (NORMAL MODE) (Power-On Default)
01H
READ
02H
WRITE
03H
04H
VERIFY
05H
ERASE PAGE
06H
ERASE ALL
81H
READBYTE
82H
WRITEBYTE
0FH
EXULOAD
F0H
ULOAD
REV. 0
Results in 4 bytes in the Flash/EE data memory,
addressed by the page address EADRH/L, being read
Reserved Command
Verifies if the data in EDATA1–4 is contained in the
page address given by EADRH/L. A subsequent read
Results in the erase of entire 4 kBytes of Flash/EE
Results in the byte in the Flash/EE data memory,
addressed by the byte address EADRH/L, being read
Results in the byte in EDATA1 being written into
Flash/EE data memory.
COMMAND DESCRIPTION
into EDATA1–4.
Results in four bytes in EDATA1–4 being written to
the Flash/EE data memory, at the page address given by
EADRH/L (0 ≤ EADRH/L < 0400H.
Note: The four bytes in the page being addressed must
be pre-erased.
of the ECON SFR will result in a 0 being read if the
verification is valid, or a nonzero value being read to
indicate an invalid verification.
Results in the Erase of the 4-byte page of Flash/EE data
memory addressed by the page address EADRH/L.
data memory.
into EDATA1. (0 ≤ EADRH/L ≤ 0FFFH).
Flash/EE data memory, at the byte address EADRH/L.
Leaves the ECON instructions to operate on the
Enters ULOAD mode, directing subsequent ECON
instructions to operate on the Flash/EE program memory.
Table VII. ECON—Flash/EE Memory Commands
–29–
Figure 20. Flash/EE Data Memory Control and Configuration
ARE GIVEN IN
ADDRESSES
BRACKETS
BYTE
3FEH
3FFH
02H
01H
00H
COMMAND DESCRIPTION
(ULOAD MODE)
Not Implemented. Use the MOVC instruction.
Results in bytes 0-255 of internal XRAM being written
to the 256 bytes of Flash/EE program memory at the
page address given by EADRH. (0 ≤ EADRH < E0H)
Note: The 256 bytes in the page being addressed must
be pre-erased.
Reserved Command
Not Implemented. Use the MOVC and MOVX
instructions to verify the WRITE in software.
Results in the 64-byte page of Flash/EE program
memory, addressed by the byte address EADRH/L
being erased. EADRL can equal any of 64 locations
within the page. A new page starts whenever EADRL
is equal to 00H, 40H, 80H, or C0H.
Results in the Erase of the entire 56 kBytes of ULOAD
Flash/EE program memory.
Not Implemented. Use the MOVC command.
Results in the byte in EDATA1 being written into
Flash/EE program memory, at the byte address
EADRH/L (0 ≤ EADRH/L ≤ DFFFH).
Enters NORMAL mode directing subsequent ECON
instructions to operate on the Flash/EE data memory.
Leaves the ECON instructions to operate on the
Flash/EE program memory.
03H
(0FFCH)
(0FF8H)
(000CH)
BYTE 1
BYTE 1
BYTE 1
(0008H)
BYTE 1
(0004H)
(0000H)
BYTE 1
BYTE 1
(0FFDH)
(000DH)
(0009H)
(0005H)
(0001H)
BYTE 2
(0FF9H)
BYTE 2
BYTE 2
BYTE 2
BYTE 2
BYTE 2
(0FFAH)
(0FFEH)
(000EH)
(000AH)
(0006H)
BYTE 3
BYTE 3
BYTE 3
BYTE 3
BYTE 3
(0002H)
BYTE 3
ADuC831
(0FFFH)
BYTE 4
(0FFBH)
(000FH)
(000BH)
(0007H)
(0003H)
BYTE 4
BYTE 4
BYTE 4
BYTE 4
BYTE 4