DK-DEV-3SL150N Altera, DK-DEV-3SL150N Datasheet - Page 9

• Manufacturer Part Number: DK-DEV-3SL150N
• Description: KIT DEVELOPMENT STRATIX III
• Manufacturer: Altera
• Series: Stratix® IIIr
• Type: FPGAr

Specifications of DK-DEV-3SL150N

• Contents: Development Platform, Cables and Software
• Silicon Manufacturer: Altera
• Core Architecture: FPGA
• Core Sub-architecture: Stratix
• Silicon Core Number: EP3S
• Silicon Family Name: Stratix III
• Kit Contents: Development Board, Cable And Accessories
• Rohs Compliant: Yes
• For Use With/related Products: EP3SL150F152
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 544-2568

Chapter 1: Stratix III Device Family Overview
Architecture Features
I/O Banks and I/O Structure
External Memory Interfaces
High-Speed Differential I/O Interfaces with DPA
© March 2010 Altera Corporation
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For more information, refer to the
chapter.
Stratix III devices contain up to 24 modular I/O banks, each of which contains 24, 32,
36, 40, or 48 I/Os. This modular bank structure improves pin efficiency and eases
device migration. The I/O banks contain circuitry to support external memory
interfaces at speeds up to 533 MHz and high-speed differential I/O interfaces meeting
up to 1.6 Gbps performance. It also supports high-speed differential inputs and
outputs running at speeds up to 800 MHz.
Stratix III devices support a wide range of industry I/O standards, including
single-ended, voltage referenced single-ended, and differential I/O standards. The
Stratix III I/O supports programmable bus hold, programmable pull-up resistor,
programmable slew rate, programmable drive strength, programmable output delay
control, and open-drain output. Stratix III devices also support on-chip series (R
on-chip parallel (R
and on-chip differential termination (R
banks. Dynamic OCT is also supported on bi-directional I/O pins in all I/O banks.
For more information, refer to the
The Stratix III I/O structure has been completely redesigned to provide flexibility and
enable high-performance support for existing and emerging external memory
standards such as DDR, DDR2, DDR3, QDR II, QDR II+, and RLDRAM II at
frequencies of up to 533 MHz.
Packed with features such as dynamic on-chip termination, trace mismatch
compensation, read/write leveling, half-rate registers, and 4-to 36-bit programmable
DQ group widths, Stratix III I/Os supply the built-in functionality required for rapid
and robust implementation of external memory interfaces. Double data-rate support
is found on all sides of the Stratix III device. Stratix III devices provide an efficient
architecture to quickly and easily fit wide external memory interfaces exactly where
you want them.
A self-calibrating soft IP core (ALTMEMPHY), optimized to take advantage of the
Stratix III device I/O, along with the Quartus II timing analysis tool (TimeQuest),
provide the total solution for the highest reliable frequency of operation across
process voltage and temperature.
For more information about external memory interfaces, refer to the
Interfaces in Stratix III Devices
Stratix III devices contain dedicated circuitry for supporting differential standards at
speeds up to 1.6 Gbps. The high-speed differential I/O circuitry supports the
following high-speed I/O interconnect standards and applications: Utopia IV, SPI-4.2,
SFI-4, 10 Gigabit Ethernet XSBI, Rapid I/O, and NPSI. Stratix III devices support 2×,
4×, 6×, 7×, 8×, and 10× SERDES modes for high-speed differential I/O interfaces and
T
) termination with auto calibration for single-ended I/O standards
chapter.
Clock Networks and PLLs in Stratix III Devices
Stratix III Device I/O Features
D
) for LVDS I/O standards on Left/Right I/O
Stratix III Device Handbook, Volume 1
chapter.
External Memory
S
) and
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