DK-DEV-3SL150N Altera, DK-DEV-3SL150N Datasheet - Page 2

• Manufacturer Part Number: DK-DEV-3SL150N
• Description: KIT DEVELOPMENT STRATIX III
• Manufacturer: Altera
• Series: Stratix® IIIr
• Type: FPGAr

Specifications of DK-DEV-3SL150N

• Contents: Development Platform, Cables and Software
• Silicon Manufacturer: Altera
• Core Architecture: FPGA
• Core Sub-architecture: Stratix
• Silicon Core Number: EP3S
• Silicon Family Name: Stratix III
• Kit Contents: Development Board, Cable And Accessories
• Rohs Compliant: Yes
• For Use With/related Products: EP3SL150F152
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 544-2568

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Stratix III Device Handbook, Volume 1
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Selectable Core Voltage, available in low-voltage devices (L ordering code suffix),
enables selection of lowest power or highest performance operation
Up to 16 global clocks, 88 regional clocks, and 116 peripheral clocks per device
Up to 12 phase-locked loops (PLLs) per device that support PLL reconfiguration,
clock switchover, programmable bandwidth, clock synthesis, and dynamic phase
shifting
Memory interface support with dedicated DQS logic on all I/O banks
Support for high-speed external memory interfaces including DDR, DDR2,
DDR3 SDRAM, RLDRAM II, QDR II, and QDR II+ SRAM on up to 24 modular
I/O banks
Up to 1,104 user I/O pins arranged in 24 modular I/O banks that support a wide
range of industry I/O standards
Dynamic On-Chip Termination (OCT) with auto calibration support on all I/O
banks
High-speed differential I/O support with serializer/deserializer (SERDES) and
dynamic phase alignment (DPA) circuitry for 1.6 Gbps performance
Support for high-speed networking and communications bus standards including
SPI-4.2, SFI-4, SGMII, Utopia IV, 10 Gigabit Ethernet XSBI, Rapid I/O, and NPSI
The only high-density, high-performance FPGA with support for 256-bit AES
volatile and non-volatile security key to protect designs
Robust on-chip hot socketing and power sequencing support
Integrated cyclical redundancy check (CRC) for configuration memory error
detection with critical error determination for high availability systems support
Built-in error correction coding (ECC) circuitry to detect and correct data errors in
M144K TriMatrix memory blocks
Nios
Support for multiple intellectual property megafunctions from Altera
functions and Altera Megafunction Partners Program (AMPP
®
II embedded processor support
Chapter 1: Stratix III Device Family Overview
© March 2010 Altera Corporation
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Features Summary
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MegaCore
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