EZ80F917050SBCG Zilog, EZ80F917050SBCG Datasheet - Page 18

• Manufacturer Part Number: EZ80F917050SBCG
• Description: BOARD ZDOTS SBC Z80ACCLAIM PLUS
• Manufacturer: Zilog
• Series: Zdots® SBCr
• Type: MCUr

Specifications of EZ80F917050SBCG

• Contents: Fully Assembled Evaluation Board
• For Use With/related Products: eZ80F91
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 269-4671

PS026102-1207
Data Bus
F91 Data
FLash
Bus
-CS1
-CS0
Clock
-RD
-WR
going into High-Z mode, that is, after the end of the eZ80F91 Read access to Flash, it
takes 8.8 ns+25 ns = 33.8 ns before Flash stops driving the data bus. At this point, the
eZ80F91 device is already well into the next bus cycle.
Consider the next cycle to be Memory Write. During the Memory Write cycle, data (out-
put) from the eZ80F91 device is valid not later than T3 = 7.5 ns, and the Write pulse is
asserted not later than 4.5 ns after the falling edge of the Clock (14.5 ns from the rising
edge if Clock is 50 MHz). It means that during T
devices drive the common Data Bus—the eZ80F91 device and Flash. In turn, data that is
being written during the Write operation might be corrupted. The part used to isolate a
slow Flash data bus from a fast eZ80F91 bus has 5.5 ns turn-off time, which reduces 25 ns
part of the T
26.3 ns, as described in the following equation:
Data being written is not corrupted because the Write pulse is not yet asserted.
Figure 4. Bus Contention without the Zdots Fast Buffer Feature
Time of contention
T6
CON
to 5.5 ns. As a result, bus contention still occurs, but its duration is not
Zdots
=
(
8.8 ns
®
SBC for eZ80AcclaimPlus!
-
Data IN
7.5 ns
+
5.5 ns
T3
CON
)
= (33.8 ns – 7.5 ns) = 26.3 ns; two
=
Bus contention
Data OUT
T4
6.8 ns
Tod
Onboard Component Description
Product Specification
™
Connectivity ASSP
14