EZ80F917050SBCG Zilog, EZ80F917050SBCG Datasheet - Page 17

• Manufacturer Part Number: EZ80F917050SBCG
• Description: BOARD ZDOTS SBC Z80ACCLAIM PLUS
• Manufacturer: Zilog
• Series: Zdots® SBCr
• Type: MCUr

Specifications of EZ80F917050SBCG

• Contents: Fully Assembled Evaluation Board
• For Use With/related Products: eZ80F91
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 269-4671

Fast Buffer (U10)
PS026102-1207
Table 3. Zdots MII Resistor Configuration (Continued)
Notes
ANEG
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
R24
IN
IN
1. MII Register 0 (Speed and Duplex Bits) must be set by a MAC to achieve a link.
2. When autonegotiation is enabled, these bits are written but will be ignored by PHY.
3. The advertised abilities of MII Register 4 cannot exceed the abilities of MII Register 1. Autonegotiation must
always be enabled.
Ethernet LEDs
(Tech[2])
OUT
OUT
OUT
OUT
OUT
OUT
R19
IN
IN
IN
IN
The Ethernet connection is provided by the HALO RJ45 connector. It consists of two
green LEDs that are located next to each other on the Zdots
data, the left LED is ON. When the PHY is transmitting data, the right LED is ON.
The Zdots has a fast buffer that (see
that occurs because of slow turn-off time of the module’s external Flash and the fast bus
turn-around time of the eZ80F91 (generic feature of the eZ80
NATIVE mode).
The problem related to bus contention when using eZ80 family of the microprocessors in
NATIVE eZ80 mode is explained below, see
to eZ80F91 Product Specification (PS0192).
Bus contention occurs when two or more devices drive a common bus. The eZ80F91’s
CS0 drives the Flash CE. After the access to Flash, CS0 is driven High a maximum of
8.8 ns after the next rising edge of the Clock (T6 in
(T
OD
) is 25 ns, which is the time from OE or CE going High to the Flash output drivers
(Tech[1])
OUT
OUT
OUT
OUT
OUT
OUT
R23
IN
IN
IN
IN
(Tech[0]) Speed Full-Duplex ANEG-EN Capabilities
OUT
OUT
OUT
OUT
OUT
R21
IN
IN
IN
IN
IN
Zdots
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
No
No
®
2
2
2
2
2
2
2
3
SBC for eZ80AcclaimPlus!
Figure 1
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
No
No
2
2
2
2
2
2
2
2
Figure 4
on page 3) exists to prevent bus contention
Figure
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
on page 14. For more details, refer
No
No
3
3
3
3
3
3
3
3
4). The Flash turn-off time
®
Onboard Component Description
. When PHY is receiving
®
family when it is used in
Product Specification
100FD/HD
™
10FD/HD
100HD,
100HD
100FD
100FD
10HD
10HD
None
None
Connectivity ASSP
All
Disabled
Disabled
Enabled
Enabled
Enabled
Enabled
Enabled
Enabled
Enabled
Enabled
ANEG
13