EVAL-ADUC842QS Analog Devices Inc, EVAL-ADUC842QS Datasheet - Page 83
EVAL-ADUC842QS
Manufacturer Part Number
EVAL-ADUC842QS
Description
KIT DEV FOR ADUC842 QUICK START
Manufacturer
Analog Devices Inc
Series
QuickStart™ Kitr
Type
MCUr
Datasheet
1.EVAL-ADUC842QS.pdf
(88 pages)
Specifications of EVAL-ADUC842QS
Contents
Evaluation Board, Power Supply, Cable, Software and Documentation
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
For Use With/related Products
ADuC842
Lead Free Status / RoHS Status
Not Compliant, Contains lead / RoHS non-compliant
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Parameter
SPI MASTER MODE TIMING (CPHA = 0)
t
t
t
t
t
t
t
t
t
t
1
SL
SH
DAV
DOSU
DSU
DHD
DF
DR
SR
SF
Characterized under the following conditions:
a. Core clock divider bits CD2, CD1, and CD0 bits in PLLCON SFR set to 0, 1, and 1, respectively, i.e., core clock frequency = 2.09 MHz.
b. SPI bit-rate selection bits SPR1 and SPR0 in SPICON SFR set to 0 and 0, respectively.
(CPOL = 0)
(CPOL = 1)
SCLOCK Low Pulse Width
SCLOCK High Pulse Width
Data Output Valid after SCLOCK Edge
Data Output Setup before SCLOCK Edge
Data Input Setup Time before SCLOCK Edge
Data Input Hold Time after SCLOCK Edge
Data Output Fall Time
Data Output Rise Time
SCLOCK Rise Time
SCLOCK Fall Time
SCLOCK
SCLOCK
MOSI
MISO
t
DOSU
t
DSU
MSB IN
1
MSB
1
t
DHD
t
SH
t
DF
Figure 92. SPI Master Mode Timing (CPHA = 0)
t
DAV
t
SL
t
DR
Rev. 0 | Page 83 of 88
BITS 6–1
BITS 6–1
LSB IN
t
SR
LSB
ADuC841/ADuC842/ADuC843
Min
100
100
t
SF
Typ
476
476
10
10
10
10
Max
50
150
25
25
25
25
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
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