ATSTK600 Atmel, ATSTK600 Datasheet - Page 12

• Manufacturer Part Number: ATSTK600
• Description: DEV KIT FOR AVR/AVR32
• Manufacturer: Atmel
• Series: AVR®r
• Type: MCUr

Specifications of ATSTK600

• Processor To Be Evaluated: AVR and AVR32
• Data Bus Width: 8 bit
• Interface Type: RS-232, USB
• Silicon Manufacturer: Atmel
• Core Architecture: AVR
• Core Sub-architecture: AVR UC3
• Silicon Core Number: STK600
• Silicon Family Name: AVR
• Kit Contents: Board
• Rohs Compliant: Yes
• For Use With/related Products: Atmel AVR Devices
• For Use With: ATSTK600-ATTINY10 - STK600-ATTINY10 SOCKET PACKAGE
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Contents: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

AVR32 Inside
Introducing the AVR32
Traditionally chip vendors have increased processing power by making processors run faster. This is a
real issue for portable devices because tuning up the clock directly increases power consumption and
reduces battery life. The approach taken by Atmel with the AVR32 is to increase the amount of processing
the processor can do internally and actually turn the clock frequency down.
The AVR32 core architecture is optimized for highest data throughput. Most RISC architectures are wast-
ing processor cycles for non productive operations like load, store or moving data, for branches, for load-
ing data which are not in the cache or waiting until a multi cycle instruction is done. All those operations
do not contribute to the execution of the application.
AVR32 AP Core Features
There are a lot of improvements which have been made to speed up the overall core performance. With the Accumulator-Cache
a new and patent method was developed which multiplies and accumulates within one clock cycle, without using an additional
port. The accumulator cache is used to store the value which has to be added.
The Pipeline also supports „Data Forwarding“. All instructions that are completed will be forwarded to the beginning of the
pipeline so they can be used for waiting instructions without needing additional cycles.
With SIMD instructions (Single Instruction/Multiple Data) the data throughput of certain DSP algorithm can be extremely ac-
celerated.
The advantage of deep pipelines is clear higher frequencies, but also they may loose performance when a jump is performed
and the pipeline has to be reloaded. Especially in cases where small nested loops have to be executed the efficiency of the pipe-
line is dramatically reduced. By memorizing the jump address the branch can be folded to zero cycle branching which is also
known as „Predictable Branching“.
One Architecture - Two Families
The first device was designed to be used in full-fledge OS like Linux. Linux supporting architectures require Memory Manage-
ment Unit for virtual address support but do have disadvantages for real-time applications. Also instruction- and data-cache
are not supporting predictable timing and response times. So Atmel decided to go two different ways: One is the AP7 (Applica-
tion Processor) which is optimized for Linux and the other is UC3 (simple for µController) which was optimized for real-time OS.
Both families will be expanded in future by new derivates.
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The UC3 family is also equipped with an extensive DSP instruction set providing high-speed signal processing by hardware. An
optimized DSP software library is supported from Atmel and can be downloaded from the Web free of charge.
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