DM240002 Microchip Technology, DM240002 Datasheet - Page 20

• Manufacturer Part Number: DM240002
• Description: BOARD DEV EXPLORER 16 44-PIN
• Manufacturer: Microchip Technology
• Series: Explorer 16 44-pinr
• Type: MCUr

Specifications of DM240002

• Contents: Explorer 16 Dev Board, PIC24FJ64GA004 and dsPIC33FJ32GP204 PIM Modules
• Processor To Be Evaluated: PIC24FJ128GA010, dsPIC33FJ256GP710
• Processor Series: PIC 24, dsPIC33
• Data Bus Width: 32 bit
• Interface Type: RS-232
• Silicon Manufacturer: Microchip
• Core Architecture: PIC, DsPIC
• Core Sub-architecture: PIC24, DsPIC33
• Silicon Core Number: PIC24F, DsPIC33F
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With/related Products: dsPIC30, dsPIC33, PIC32, PIC24FJ, PIC24HJ
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

44-Pin Demo Board User’s Guide
DS41296B-page 16
Increment or Decrement a File Register
EXAMPLE 3-3:
The GOTO Loop (in Example 3-3) backs up and does it again. This loop takes 3
instruction times; one for the decrement and two for the GOTO (see note) and the
counter will force it to go around 256 times, which takes it a total of 768 instruction times
(768 μs) to execute.
Even that is still too fast for the eye to see. It can be slowed down even more by adding
a second loop around this one.
The inner loop still takes 768 μs plus 3 for the outer loop, but now it’s executed another
256 times, (768 + 3) * 256 = 197376 μs = 0.197s.
Open Blink.asm and build the lesson. Next, import the hex file into the PICkit 2 and
program the device. Note the LED now flashes at about a 2.5 Hz rate.
Note:
Short Loop
Loop
Long Loop
Loop
The INCFSZ and DECFSZ instructions add or subtract one from the contents of
the file register and skips the next instruction when the result is zero. One use is
in the delay loop as shown in Example 3-3.
CLRF Clears the counter location.
DECFSZ Decrements the location, and if the result is zero, the next instruction is
skipped.
CLRF
DECFSZ
GOTO
CLRF
CLRF
DECFSZ
GOTO
DECFSZ
GOTO
GOTO instructions take two instructions due to the pipelined design of the
processor. The processor fetches the next instruction while executing the
current instruction. When a program branch occurs, the fetched instruction
is not executed.
Delay
Delay,f
Loop
Delay1
Delay2
Delay1,f
Loop
Delay2,f
Loop
DELAY LOOP
© 2007 Microchip Technology Inc.