ATAVRQTOUCHX Atmel, ATAVRQTOUCHX Datasheet - Page 173

• Manufacturer Part Number: ATAVRQTOUCHX
• Description: BOARD EVAL CAPACITIVE TOUCH
• Manufacturer: Atmel
• Series: QTouch™r

Specifications of ATAVRQTOUCHX

• Sensor Type: Touch, Capacitive
• Sensing Range: 1 Slider, 1 Wheel, 2 Buttons
• Interface: USB
• Voltage - Supply: 5V, USB
• Embedded: Yes, MCU, 8-Bit
• Utilized Ic / Part: AT90USB1287, ATxmega128A1
• Silicon Manufacturer: Atmel
• Silicon Family Name: ATxmega
• Kit Contents: Board
• Svhc: No SVHC (15-Dec-2010)
• Core Architecture: AVR
• Core Sub-architecture: AVR19
• Kit Features: One Slider, One Wheel And 2
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Sensitivity: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

7.5.2.1.2
When SNS and SNSK pins are connected to the same port, the even pin numbers will be used as
SNS pins and the odd pins will be used as the SNSK pins.
7.5.2.2
The libraries internally need SNS_array and SNSK_array masks. These masks need to be
defined under Macro QTOUCH_STUDIO_MASKS as per the following rules given below:
1.
Channel0 and Channel2.And SNS_array[1] and SNSK_array[1] mask is used for configuring the
Channel1 and Channel3.And In case of Intraport SNS_array[0] and SNSK-array[0] are used for
all the four channels configured based on enabled bits in SNS_array[0] and SNSK-array[0].
2. The channel numbers are allocated based on enabled SNS pins starting from LSBBit.
In case of Interport, Keys on adjacent channels should be placed on different masks. Channel0
and Channel1 should be on different SNS/SNSK masks ie channel0 on
SNS_array[0]/SNSK_array[0] and channel1 on SNS_array[1]/ SNSK_array[1].
But in case of Intraport, Keys on adjacent channels should be placed on same masks. Channel0
and Channel2 should be on same mask ie SNS_array[0]/SNSK_array[0] and Channel1 and
Channel3 on SNS_array[1]/ SNSK_array[1].
7.5.2.2.1
1. Enable the Bit0 in SNS_array[0] and Bit0 in SNSK_array[0] mask when enabling Channel0.
2. Enable the Bit1 in SNS_array[1] and Bit1 in SNSK_array[1] mask when enabling Channel1.
3. Enable the Bit2 in SNS_array[0] and Bit2 in SNSK_array[0] mask when enabling Channel2.
4. Enable the Bit3 in SNS_array[1] and Bit3 in SNSK_array[1] mask when enabling Channel3.
Example 1:
In a 4 channel library, two keys on channel 0 and 3 are enabled.SNS on Port A and SNSK on
Port B .Channel0 will A0B0 and Channel3 will be A3B3.
The SNS and SNSK masks will be
SNS_array[0]=0x01;
SNS_array[1]=0x08;
SNSK_array[0]=0x01;
SNSK_array[1]=0x08;
•
•
•
The number of channels supported will be limited 4 channels
For e.g., for a 4 channel configuration where the SNS and SNSK pins are connected to
Port B, the port pins 0&1 are used for channel 0.
The channel number is derived from the position of the pins used for SNS and SNSK
lines for any channel.
o
In case of Interport, SNS_array[0] and SNSK_array[0] mask is used for configuring the
Rules For Configuring SNS and SNSK masks for 2K Devices
Configuring SNS and SNSK masks in case of Interport:
Channel numbering when routing SNS and SNSK pins to the same port
For e.g., pins 4 and 5 are connected to a SNS/SNSK pair and the channel number
associated with the SNS/SNSK pin is 2.
channel number = floor( [SNS(or SNSK) pin number] / 2 )
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