AD8250-EVALZ Analog Devices Inc, AD8250-EVALZ Datasheet
AD8250-EVALZ
Specifications of AD8250-EVALZ
Related parts for AD8250-EVALZ
AD8250-EVALZ Summary of contents
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... The AD8250 user interface consists of a parallel port that allows users to set the gain in one of two ways (see Figure 1). A 2-bit word sent via a bus can be latched using the WR input. An alternative is to use the transparent gain mode where the state of the logic levels at the gain port determines the gain ...
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... AD8250 TABLE OF CONTENTS Features .............................................................................................. 1 Applications....................................................................................... 1 General Description ......................................................................... 1 Functional Block Diagram .............................................................. 1 Revision History ............................................................................... 2 Specifications..................................................................................... 3 Timing Diagram ........................................................................... 5 Absolute Maximum Ratings............................................................ 6 Maximum Power Dissipation ..................................................... 6 ESD Caution.................................................................................. 6 Pin Configuration and Function Descriptions............................. 7 Typical Performance Characteristics ............................................. 8 Theory of Operation ...................................................................... 15 Gain Selection ............................................................................. 15 Power Supply Regulation and Bypassing ................................ 17 REVISION HISTORY 11/10— ...
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... AD8250 Unit nV/√Hz nV/√Hz nV/√Hz nV/√Hz μV p-p μV p-p μV p-p μV p-p pA/√Hz pA p-p μV μV μV/°C μ ...
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... AD8250 Parameter Settling Time 0.001 Slew Rate Total Harmonic Distortion GAIN Gain Range Gain Error Gain Nonlinearity Gain vs. Temperature INPUT Input Impedance Differential Common Mode Input Operating Voltage Range Over Temperature OUTPUT Output Swing Over Temperature Short-Circuit Current REFERENCE INPUT R IN ...
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... TIMING DIAGRAM Figure 3. Timing Diagram for Latched Gain Mode (See the Timing for Latched Gain Mode Section) Conditions T = −40°C to +85° WR-HIGH WR-LOW A0, A1 Rev Page Min Typ Max ±5 ±15 4.1 4.5 3.7 4.5 4.5 −40 +85 AD8250 Unit °C ...
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... Exposure to absolute maximum rating conditions for extended periods may affect device reliability. MAXIMUM POWER DISSIPATION The maximum safe power dissipation in the AD8250 package is limited by the associated rise in junction temperature (T the die. The plastic encapsulating the die locally reaches the junction temperature. At approximately 140° ...
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... Figure 5. Pin Configuration Description Inverting Input Terminal. True differential input. Digital Ground. Negative Supply Terminal. Gain Setting Pin (LSB). Gain Setting Pin (MSB). Write Enable. Output Terminal. Positive Supply Terminal. Reference Voltage Terminal. Noninverting Input Terminal. True differential input. Rev Page AD8250 ...
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... AD8250 TYPICAL PERFORMANCE CHARACTERISTICS T = 25° +15 V, −V = − 1400 1200 1000 800 600 400 200 0 –120 –90 –60 – CMRR (µV/V) Figure 6. Typical Distribution of CMRR 350 300 250 200 150 100 50 0 –200 –150 –100 – OFFSET VOLTAGE RTI (µV) Figure 7 ...
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... Figure 17. Change in Offset Voltage, RTI vs. Warmup Time Rev Page AD8250 100 1k 10k 100k FREQUENCY (Hz) Figure 15. Positive PSRR vs. Frequency, RTI 100 1k 10k 100k FREQUENCY (Hz) Figure 16. Negative PSRR vs. Frequency, RTI 0.1 1 WARMUP TIME (Minutes ...
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... AD8250 – – –10 –15 –40 –25 – TEMPERATURE (°C) Figure 18. Input Bias Current and Offset Current vs. Temperature 140 120 100 100 1k FREQUENCY (Hz) Figure 19. CMRR vs. Frequency 140 120 100 100 1k FREQUENCY (Hz) Figure 20. CMRR vs. Frequency, 1 kΩ Source Imbalance 110 125 10k ...
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... OUTPUT VOLTAGE (V) 0V, +13.8V –14.1V, +13.6V +13.6V, +13. ±15V S +0V, +3.5V –4.2V, +2.2V +4.3V, +2. ±5V S –4.2V, –2.0V +4.3V, –2.1V 0V, –4.1V –14.1V, –13.6V +13.6V, –13.1V 0V, –14V –12 –8 – OUTPUT VOLTAGE ( – –15 –10 – COMMON-MODE VOLTAGE (V) AD8250 ...
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... AD8250 +V S –1 +85°C +125°C +25°C –2 +2 +85°C +1 +125°C – SUPPLY VOLTAGE (±V Figure 30. Input Voltage Limit vs. Supply Voltage FAULT CONDITION (OVER DRIVEN INPUT) (OVER DRIVEN INPUT –5 –10 –15 –16 –12 –8 –4 0 DIFFERENTIAL INPUT VOLTAGE (V) Figure 31. Fault Current Draw vs. Input Voltage 10, R ...
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... Figure 39. Large Signal Pulse Response and Settling Time 5V/DIV 0.002%/DIV 2µs/DIV Figure 40. Large Signal Pulse Response and Settling Time 20mV/DIV 2µs/DIV Rev Page AD8250 605ns TO 0.01% 635ns TO 0.001% 2µs/DIV TIME (µ kΩ L 648ns TO 0.01% 685ns TO 0.001% 2µs/DIV TIME (µ ...
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... AD8250 20mV/DIV TIME (µs) Figure 42. Small Signal Response kΩ 100 20mV/DIV TIME (µs) Figure 43. Small Signal Response kΩ 100 20mV/DIV TIME (µs) Figure 44. Small Signal Response 10 kΩ 100 –50 –55 –60 –65 –70 –75 –80 –85 –90 –95 –100 –105 – ...
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... A parallel interface allows users to digitally program gains and 10. Gain control is achieved by switching resistors in an internal, precision resistor array (as shown in Figure 47). Although the AD8250 has a voltage feedback topology, the gain bandwidth product increases for gains and 5 because each gain has its own frequency compensation. ...
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... Some applications have multiple programmable devices such as multiplexers or other programmable gain instrumentation amplifiers on the same PCB. In such cases, devices can share a data bus. The gain of the AD8250 can be set using latch, allowing other devices to share A0 and A1. schematic using this method, known as latched gain mode. The ...
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... S Figure 51. Supply Decoupling, REF, and Output Referred to Ground INPUT BIAS CURRENT RETURN PATH The AD8250 input bias current must have a return path to its local analog ground. When the source, such as a thermocouple, cannot provide a return current path, one should be created (see Figure 52). ...
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... For example, a voltage source can be tied to the REF pin to level shift the output so that the AD8250 can interface with a single-supply ADC. The allowable reference voltage range is a function of the gain, common-mode input, and supply voltages. The REF pin should not exceed either +V or − ...
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... AD7612. Selecting too small a resistor improves the correlation between the voltage at the output of the AD8250 and the voltage at the input of the AD7612 but may destabilize the AD8250. A trade- off must be made between selecting a resistor small enough to maintain accuracy and large enough to maintain stability. 10µ ...
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... High resolution ADCs often require a differential input. In other cases, transmission over a long distance can require differential signals for better immunity to interference. Figure 57 shows how to configure the AD8250 to output a differential signal amp, the AD817, is used in an inverting topology to create a differential voltage. V midpoint according to the equation shown in the figure ...
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... S2B A0 806Ω –CH1 S1B 0.1µF –12V JMP Figure 59. Schematic of ADG1209, AD8250, and AD7612 in the AD825x DAQ Demo Board Figure 58. FFT of the AD825x DAQ Demo Board Using the AD8250, +12V –12V + + 10µF 10µF GND DGND JMP DGND 2 DGND 6 0Ω ...
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... COPLANARITY ORDERING GUIDE 1 Model Temperature Range AD8250ARMZ –40°C to +85°C AD8250ARMZ-RL –40°C to +85°C AD8250ARMZ-R7 –40°C to +85°C AD8250-EVALZ RoHS Compliant Part. 3.10 3.00 2.90 5. 4.90 4. 0.50 BSC 15° MAX 1.10 MAX 6° ...
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... NOTES Rev Page AD8250 ...
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... AD8250 NOTES ©2007–2010 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. D06288-0-11/10(B) Rev Page ...