LP38856-1.2EVAL National Semiconductor, LP38856-1.2EVAL Datasheet - Page 10

• Manufacturer Part Number: LP38856-1.2EVAL
• Description: BOARD EVALUATION LP38856-1.2
• Manufacturer: National Semiconductor
• Series: PowerWise®r

Specifications of LP38856-1.2EVAL

• Channels Per Ic: 1 - Single
• Voltage - Output: 1.2V
• Current - Output: 3A
• Voltage - Input: 3 ~ 5.5V
• Regulator Type: Positive Fixed
• Operating Temperature: -40°C ~ 125°C
• Board Type: Fully Populated
• Utilized Ic / Part: LP38856
• Lead Free Status / RoHS Status: Not applicable / Not applicable

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Application Information
EXTERNAL CAPACITORS
To assure regulator stability, capacitors are required on the
input, output and bias pins as shown in the Typical Application
Circuit.
Output Capacitor
A minimum output capacitance of 10 µF, ceramic, is required
for stability. The amount of output capacitance can be in-
creased without limit. The output capacitor must be located
less than 1 cm from the output pin of the IC and returned to
the device ground pin with a clean analog ground.
Only high quality ceramic types such as X5R or X7R should
be used, as the Z5U and Y5F types do not provide sufficient
capacitance over temperature.
Tantalum capacitors will also provide stable operation across
the entire operating temperature range. However, the effects
of ESR may provide variations in the output voltage during
fast load transients. Using the minimum recommended 10 µF
ceramic capacitor at the output will allow unlimited capaci-
tance, Tantalum and/or Aluminum, to be added in parallel.
Input Capacitor
The input capacitor must be at least 10 µF, but can be in-
creased without limit. It's purpose is to provide a low source
impedance for the regulator input. A ceramic capacitor, X5R
or X7R, is recommended.
Tantalum capacitors may also be used at the input pin. There
is no specific ESR limitation on the input capacitor (the lower,
the better).
Aluminum electrolytic capacitors can be used, but are not
recommended as their ESR increases very quickly at cold
temperatures. They are not recommended for any application
where the ambient temperature falls below 0°C.
Bias Capacitor
The capacitor on the bias pin must be at least 1 µF. It can be
any good quality capacitor (ceramic is recommended).
INPUT VOLTAGE
The input voltage (V
that will be regulated down to a lower voltage, which is applied
to the load. The input voltage must be at least V
and no higher than whatever value is used for V
BIAS VOLTAGE
The bias voltage (V
required to bias the control circuitry and provide gate drive for
the N-FET pass transistor. The bias voltage must be in the
range of 3.0V to 5.5V to ensure proper operation of the device.
UNDER VOLTAGE LOCKOUT
The bias voltage is monitored by a circuit which prevents the
device from functioning when the bias voltage is below the
Under-Voltage Lock-Out (UVLO) threshold of approximately
2.45V.
As the bias voltage rises above the UVLO threshold the de-
vice control circuitry become active. There is approximately
150 mV of hysteresis built into the UVLO threshold to provide
noise immunity.
When the bias voltage is between the UVLO threshold and
the Minimum Operating Rating value of 3.0V the device will
be functional, but the operating parameters will not be within
the guaranteed limits.
BIAS
IN
) is the high current external voltage rail
) is a low current external voltage rail
BIAS
OUT
.
+ V
DO
,
10
SUPPLY SEQUENCING
There is no requirement for the order that V
applied or removed. However, the output voltage cannot be
guaranteed until both V
guaranteed operating values.
If used in a dual-supply system where the regulator load is
returned to a negative supply, the output pin must be diode
clamped to ground. A Schottky diode is recommend for this
diode clamp.
REVERSE VOLTAGE
A reverse voltage condition will exist when the voltage at the
output pin is higher than the voltage at the input pin. Typically
this will happen when V
tinues to hold a sufficient charge such that the input to output
voltage becomes reversed.
The NMOS pass element, by design, contains no body diode.
This means that, as long as the gate of the pass element is
not driven, there will not be any reverse current flow through
the pass element during a reverse voltage event. The gate of
the pass element is not driven when V
threshold.
When V
is active and will attempt to regulate the output voltage. Since
the input voltage is less than the output voltage the control
circuit will drive the gate of the pass element to the full V
potential when the output voltage begins to fall. In this condi-
tion, reverse current will flow from the output pin to the input
pin, limited only by the R
output to input voltage differential. This condition is outside
the guaranteed operating range and should be avoided.
ENABLE OPERATION
The Enable pin (EN) provides a mechanism to enable, or dis-
able, the regulator output stage. The Enable pin has an
internal pull-up, through a typical 180 kΩ resistor, to V
If the Enable pin is actively driven, pulling the Enable pin
above the V
lator output on, while pulling the Enable pin below the V
threshold will turn the regulator output off. There is approxi-
mately 100 mV of hysteresis built into the Enable threshold
provide noise immunity.
If the Enable function is not needed this pin should be left
open, or connected directly to V
open, stray capacitance on this pin must be minimized, oth-
erwise the output turn-on will be delayed while the stray
capacitance is charged through the internal resistance (r
POWER DISSIPATION AND HEAT-SINKING
A heat-sink may be required depending on the maximum
power dissipation and maximum ambient temperature of the
application. Under all possible conditions, the junction tem-
perature must be within the range specified under operating
conditions.
The total power dissipation of the device is the sum of three
different points of dissipation in the device.
The first part is the power that is dissipated in the NMOS pass
element, and can be determined with the formula:
The second part is the power that is dissipated in the bias and
control circuitry, and can be determined with the formula:
BIAS
is above the UVLO threshold the control circuitry
EN
P
D(PASS)
threshold of 1.25V (typical) will turn the regu-
= (V
IN
IN
DS(ON)
is abruptly taken low and C
IN
and V
- V
OUT
of the pass element and the
BIAS
BIAS
) × I
. If the Enable pin is left
are within the range of
BIAS
OUT
is below the UVLO
IN
or V
OUT
BIAS
BIAS
con-
EN
BIAS
are
(1)
.
EN
).