MAX5774EVKIT+ Maxim Integrated Products, MAX5774EVKIT+ Datasheet - Page 18

• Manufacturer Part Number: MAX5774EVKIT+
• Description: KIT EVAL FOR MAX5774
• Manufacturer: Maxim Integrated Products

Specifications of MAX5774EVKIT+

• Number Of Dac's: 32
• Number Of Bits: 14
• Outputs And Type: 32, Single Ended
• Data Interface: Serial
• Settling Time: 20µs
• Dac Type: Voltage
• Voltage Supply Source: Analog and Digital
• Operating Temperature: 0°C ~ 85°C
• Utilized Ic / Part: MAX5774
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

GAIN = 10/3 for the MAX5773/MAX5774/MAX5775.
The MAX5773/MAX5774/MAX5775 feature an active-
low LDAC input that allows the outputs (OUT_) to
update asynchronously. Keep LDAC high during nor-
mal operation (when the device is controlled only
through the serial interface). Drive LDAC low to simulta-
neously update all DAC outputs with data from their
respective input registers. Figure 2 shows the LDAC
timing with respect to OUT_.
A software command can also perform the LDAC oper-
ation. To initiate LDAC by software, set control bits
C3–C0 = 0010, address bits A5–A0 = 111111, and all
data bits to don’t care. See Table 3 for the data format.
This operation updates all DAC outputs simultaneously.
The software load-DAC command for all channels does
not affect the offset DAC.
The MAX5773/MAX5774/MAX5775 feature a software
MAC-bypass command that loads data into the DAC
directly from DIN. Software MAC-bypass loads one DAC,
a pair of DACs, or all 32 DACs with a data word (D13–D0
and S1, S0) entered at DIN and the selected DAC out-
put(s) are simultaneously updated. Software MAC-
bypass bypasses gain and offset calibration, sending
the input data directly to the DAC register immediately
updating the selected DAC outputs. After executing
MAC-bypass on a channel(s), previously calibrated data
can be reloaded into the DAC by executing software
load-DAC or hardware LDAC (see Figure 4). Using soft-
ware MAC-bypass, the DAC output(s) can be set to the
ground-sense value or any arbitrary value within the DAC
output voltage range.
To activate software MAC-bypass, set control bits
C3–C0 = 0111. The address bits (A5–A0) select the
DAC(s) to be updated and the data bits (D13–D0) con-
trol the DAC output voltage value. Table 4 shows the
input data format for the software-controlled MAC-
bypass command.
The MAX5773/MAX5774/MAX5775 feature an active-
low RESET logic input that asynchronously sets all the
registers to code 0000h (power-up state). The serial
interface can also issue a software-reset command.
Setting the control bits C3–C0 = 1111 performs the
same function as driving the logic input RESET low.
Table 5 shows the reset data format for the software-
controlled reset command. The software reset does not
work in daisy-chain mode. Reprogram the offset DAC
after asserting a software or hardware reset.
32-Channel, 14-Bit, Voltage-Output
DACs with Serial Interface
18
______________________________________________________________________________________
Load-DAC ( LDAC ) Input
Software MAC-Bypass
Reset ( RESET )
The MAX5773/MAX5774/MAX5775 allow channel updates
either individually or in pairs. This is achieved by dividing
the 32 channels into two channel banks, with 16 channels
in each bank. Channel bank 0 contains output channels
OUT0–OUT15 and channel bank 1 contains channels
OUT16–OUT31. A channel from bank 0 is paired with a
channel from bank 1 and is ordered as OUT0:OUT16,
OUT1:OUT17...OUT14:OUT30, OUT15:OUT31.
A 3-wire SPI-/QSPI-/MICROWIRE- and DSP-compatible
serial interface controls the MAX5773/MAX5774/
MAX5775. The interface requires a
Table 4. MAC-Bypass Data Format
* S1 = S0 = 0 for proper 14-bit operation.
Table 5. Reset Data Format
* S1 = S0 = 0 for proper 14-bit operation.
Table 6. Serial Data Format
* S1 = S0 = 0 for proper 14-bit operation.
Figure 4. MAC-Bypass Functional Diagram
CONTROL
CONTROL
CONTROL
C3–C0
REGISTER
C3–C0
C3–C0
DIN
BITS
INPUT_
1111
BITS
0111
BITS
MSB
OFFSET
GAIN
*
See Figure 3
ADDRESS
ADDRESS
ADDRESS
XXXXXX
A5–A0
A5–A0
BITS
A5–A0
BITS
BITS
MAC-BYPASS
+
DATA REGISTER
CALIBRATED
XXXXXXXXXX
D13–D0 and
D13–D0 and
DATA BITS
DATA BITS
D13–D0 and
DATA BITS
D13–D0,
XXXX00
S1, S0*
S1, S0*
S1, S0*
S1, S0*
LDAC
Serial Interface
REGISTER
DAC_
DON’T-CARE
DON’T-CARE
6 Don’t-Care
6 Don’t-Care
CARE BITS
XXXXXX
6 DON’T-
XXXXXX
XXXXXX
BITS
BITS
Bits
Bits
LSB
DAC_