MAX5774EVKIT+ Maxim Integrated Products, MAX5774EVKIT+ Datasheet - Page 16

• Manufacturer Part Number: MAX5774EVKIT+
• Description: KIT EVAL FOR MAX5774
• Manufacturer: Maxim Integrated Products

Specifications of MAX5774EVKIT+

• Number Of Dac's: 32
• Number Of Bits: 14
• Outputs And Type: 32, Single Ended
• Data Interface: Serial
• Settling Time: 20µs
• Dac Type: Voltage
• Voltage Supply Source: Analog and Digital
• Operating Temperature: 0°C ~ 85°C
• Utilized Ic / Part: MAX5774
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

be accessed as a pair (see Figure 3 for pairing of out-
put channels).
The ground-sense input voltage range (V
is -0.5V to +0.5V with respect to AGND. V
to the output voltage with unity gain. Ensure that the
resulting output voltage is within the valid output volt-
age range set by the power supplies. Refer to the
Output Amplifiers (OUT0–OUT31) section for the effect
of the ground-sense inputs on the DAC outputs.
The MAX5773/MAX5774/MAX5775 feature an offset
DAC that determines the output voltage range. While
each device provides an allowable output voltage
range, the offset DAC determines the endpoint voltages
of the range. Table 1 shows the offset DAC code nec-
essary for each device’s output-voltage range.
The MAX5773/MAX5774/MAX5775 offset DAC can be
programmed with any of the three output voltage ranges.
The specifications in the Electrical Characteristics table
are only guaranteed (production tested) for the offset
code associated with each particular part number.
The offset DAC is summed with the GS_ input voltage
(see the Functional Diagram ). Any change in the offset
DAC affects all 32 DACs.
The offset DAC is also double buffered with an input
and DAC register.
Software commands for the MAC-bypass for all chan-
nels and load-DAC for all channels do not affect the off-
set DAC.
The data format for writing to the offset DAC is: control
bits C3–C0 = 0011, address bits A5–A0 = 110000, 14
data bits (and S1, S0), and 6 don’t-care bits as shown
in Table 2.
32-Channel, 14-Bit, Voltage-Output
DACs with Serial Interface
Figure 2. LDAC Timing
16
______________________________________________________________________________________
LDAC
OUT_
Offset DAC
GS1
GS
is added
t
or V
LDAC
GS2
)
All DAC outputs are internally buffered. The internal
buffers provide gain, improved load regulation, and
glitch suppression for the DAC outputs. The output
buffers slew at 1V/µs and can drive 10kΩ in parallel
with 100pF. The output buffers are powered by AV
and V
voltage range of the device.
The input code, the voltage reference, the offset DAC
output, the voltage on GS1 (or GS2), and the gain of the
output amplifier determine the output voltage. Calculate
V
Table 2. Offset DAC Input Data Format
* S1 = S0 = 0 for proper 14-bit operation.
Table 3. Software Load-DAC Input Data
Format
* S1 = S0 = 0 for proper 14-bit operation.
V
CONTROL
OUT
CONTROL
OUT
C3–C0
C3–C0
BITS
0011
BITS
0010
SS
as follows:
=
GAIN V
. AV
t
S
×
CC
Output Amplifiers (OUT0–OUT31)
REF
ADDRESS
and V
ADDRESS
110000
A5–A0
111111
A5–A0
BITS
×
BITS
(
DAC CODE OFFSET DAC CODE
SS
determine the maximum output
2
14
XXXXXXXXXX
D13–D0 and
DATA BITS
See Table 1
D13–D0 and
DATA BITS
−
S1, S0*
XXXX00
S1, S0*
±0.5 LSB
DON’T-CARE
DON’T-CARE
6 Don’t-Care
6 Don’t-Care
XXXXXX
XXXXXX
BITS
BITS
Bits
Bits
)
+
V
GS
CC
_