CDB-43L21 Cirrus Logic Inc, CDB-43L21 Datasheet - Page 22

• Manufacturer Part Number: CDB-43L21
• Description: EVAL BOARD FOR CS43L21
• Manufacturer: Cirrus Logic Inc

Specifications of CDB-43L21

• Number Of Dac's: 2
• Number Of Bits: 24
• Outputs And Type: 2, Single Ended
• Sampling Rate (per Second): 96k
• Data Interface: I²C, SPI™
• Dac Type: Voltage
• Voltage Supply Source: Analog and Digital
• Operating Temperature: -10°C ~ 70°C
• Utilized Ic / Part: CS43L21
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 598-1282; CDB-43L21

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4. APPLICATIONS
4.1
4.1.1
4.1.2
4.1.3
4.1.4
4.1.5
4.1.6
Overview
Architecture
The CS43L21 is a highly integrated, low power, 24-bit audio D/A comprised of stereo digital-to-analog
converters (DAC) designed using multi-bit delta-sigma techniques. The DAC operates at an oversampling
ratio of 128Fs. The D/A operates in one of four sample rate speed modes: Quarter, Half, Single and Dou-
ble. It accepts and is capable of generating serial port clocks (SCLK, LRCK) derived from an input Master
Clock (MCLK).
Line & Headphone Outputs
The analog output portion of the D/A includes a headphone amplifier capable of driving headphone and
line-level loads. An on-chip charge pump creates a negative headphone supply allowing a full-scale out-
put swing centered around ground. This eliminates the need for large DC-Blocking capacitors and allows
the amplifier to deliver more power to headphone loads at lower supply voltages. Eight gain settings for
the headphone amplifier are available.
Signal Processing Engine
A signal processing engine is available to process serial input D/A data before output to the DAC. The
D/A data has independent volume controls and mixing functions such as mono mixes and left/right chan-
nel swaps. A Tone Control provides bass and treble at four selectable corner frequencies. An automatic
level control provides limiting capabilities at programmable attack and release rates, maximum thresholds
and soft ramping. A 15/50 µs de-emphasis filter is also available at a 44.1 kHz sample rate.
Beep Generator
A beep may be generated internally at select frequencies across approximately two octave major scales
and configured to occur continuously, periodically or at single time intervals controlled by the user. Volume
may be controlled independently.
Device Control (Hardware or Software Mode)
In Software Mode, all functions and features may be controlled via a two-wire I²C or three-wire SPI control
port interface. In Hardware Mode, a limited feature set may be controlled via stand-alone control pins.
Power Management
Two Software Mode control registers provide independent power-down control of the DAC, allowing op-
eration in select applications with minimal power consumption.
CS43L21
DS723A1