LM5072EVAL National Semiconductor, LM5072EVAL Datasheet - Page 8

• Manufacturer Part Number: LM5072EVAL
• Description: BOARD EVALUATION LM5072
• Manufacturer: National Semiconductor
• Series: PowerWise®r

Specifications of LM5072EVAL

• Main Purpose: Special Purpose DC/DC, Power Over Ethernet
• Outputs And Type: 1, Isolated
• Power - Output: 9.9W
• Voltage - Output: 3.3V
• Current - Output: 3A
• Voltage - Input: 38 ~ 60V
• Regulator Topology: Flyback
• Frequency - Switching: 250kHz
• Board Type: Fully Populated
• Utilized Ic / Part: LM5072
• Lead Free Status / RoHS Status: Not applicable / Not applicable

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Performance Characteristics
Horizontal Resolution: 5 ms/Div.
Trace 1: VOUT, cross-regulating VCC after output regulation
is established. 2V/Div.
Trace 2: VCC, first regulated by startup regulator at 7.6V,
then elevated by auxiliary winding to 11V. 2V/Div.
Trace 3: Input Current, 0.5A/Div.
AUXILIARY INPUT POWER UP SEQUENCE
The FAUX input power up sequence is similar to that of the
PoE input, with the exception that the 38V UVLO release
threshold is overridden when the ICL_FAUX pin is pulled up.
The RAUX input power up sequence is simpler:
1. Auxiliary application quickly charges the input capaci-
2. When the V
3. As the switching regulator achieves regulation, the aux-
Figures 6 and 7 shows the FAUX and RAUX input power up
sequence, respectively.
(Continued)
tors. There should not be any overshoot observed as the
series resistors should limit the inrush.
the PWM controller begins.
iliary winding will raise the V
thus shutting down the internal regulator and increasing
efficiency.
FIGURE 5. VCC During Startup
CC
regulator establishes 7.6V, soft start of
CC
voltage to about 10V,
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Horizontal Resolution: 5 ms/Div.
Trace 1: VOUT, 2V/Div.
Trace 2: VCC, 5V/Div.
Trace 3: Input Current, 0.5A/Div.
Horizontal Resolution: 5 ms/Div.
Trace 1: VOUT, 2V/Div.
Trace 2: VCC, 5V/Div.
Trace 3: Input Current, 0.5A/Div.
Figure 8 shows the normal 3.3V output voltage startup,
along with the SS pin for reference.
FIGURE 7. Normal RAUX input Startup Sequence
FIGURE 6. Normal FAUX input Startup Sequence
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