LM5072EVAL National Semiconductor, LM5072EVAL Datasheet - Page 5

• Manufacturer Part Number: LM5072EVAL
• Description: BOARD EVALUATION LM5072
• Manufacturer: National Semiconductor
• Series: PowerWise®r

Specifications of LM5072EVAL

• Main Purpose: Special Purpose DC/DC, Power Over Ethernet
• Outputs And Type: 1, Isolated
• Power - Output: 9.9W
• Voltage - Output: 3.3V
• Current - Output: 3A
• Voltage - Input: 38 ~ 60V
• Regulator Topology: Flyback
• Frequency - Switching: 250kHz
• Board Type: Fully Populated
• Utilized Ic / Part: LM5072
• Lead Free Status / RoHS Status: Not applicable / Not applicable

Input UVLO and UVLO Hysteresis
The input Under Voltage Lock-Out (UVLO) is an integrated
function of the LM5072. The UVLO release threshold is set
to approximately 38.5V (at the pins of the IC) and the UVLO
hysteresis is approximately 7V.
Inrush and DC Current Limit
Programming
The LM5072 allows the user to independently program the
inrush and DC current limits of the internal Hot Swap MOS-
FET. The evaluation board sets the inrush limit to the default
150 mA by leaving R19 unpopulated, and the DC current
limit to the default 440 mA by leaving the DCCL pin open
(R23 not populated). In applications where it is desirable to
adjust these values, install R19 and R23, respectively, ac-
cording to the recommendations in the LM5072 datasheet.
Please note that by leaving the DCCL pin open, the default
440 mA DC current limit will be elevated to 550 mA during
FAUX operation. When R23 is used to program the DC
current limit, it applies to both PoE and FAUX power modes,
and it should be considered a “firm limit”, i.e. independent of
operating mode.
FAUX Power Option
For the FAUX power option, the ICL_FAUX pin of the
LM5072 senses the FAUX input voltage through D7 and R6.
When the current flowing into the ICL_FAUX pin is greater
than 50 µA at 8.5V nominal, it will establish a state at the
ICL_FAUX pin that forces UVLO release in order to allow
operation at an auxiliary input voltage as low as 18V (17V
seen by the VIN pin of the LM5072 IC). One should not try to
use the ICL_FAUX as a stable, accurate UVLO threshold,
the front auxiliary supply should pull the pin up well past the
voltage and current thresholds.
It should be pointed out that the minimum operative FAUX
input voltage for the maximum output current is 24V. This is
mainly limited by the default 540 mA FAUX input DC current
limit of the LM5072’s internal hot swap MOSFET. By lower-
ing the FAUX input voltage, the input current will exceed the
said limit unless the output current is reduced accordingly.
If the FAUX power option is not used in a new design, delete
C1, D3, D7, R6, and J2 from the circuit to reduce the BOM
cost.
RAUX Power Option
For the rear auxiliary power option, the RAUX pin of the
LM5072 senses the RAUX input voltage through R13. When
the current flowing into the RAUX pin is greater than 20 µA at
2.5V nominal, it will establish a state at the RAUX pin that
forces switching regulator controller operation at input volt-
ages as low as 10V (9V seen by the pins of the LM5072 IC).
When the current flowing into the RAUX pin is greater than
250 µA at 6V nominal, which is the preset configuration of
the evaluation board, auxiliary dominance is selected. Dur-
ing auxiliary dominance, the RAUX power source will always
supply the current to the PD regardless if PoE power is
present or not. This is accomplished by forcing a shut down
of the hot swap MOSFET. If the PSE has implemented DC
Maintain Power Signature, it will remove the 48V supply thus
freeing up power to be allocated to other ports. If only AC
Maintain Power Signature is implemented, the PSE may or
may not remove power. Note that auxiliary non-dominance
does not imply PoE dominance. PoE dominance is very
5
difficult to achieve without additional circuitry. Contact Na-
tional Semiconductor for a schematic of a robust PoE domi-
nant solution.
Because the LM5072’s input hot swap feature is not appli-
cable to the RAUX input, two 2Ω resistors (R1 and R2) in
parallel are used to achieve transient protection. Unlimited
inrush currents can wear on board traces, connector con-
tacts, and various board components, as well as create
dangerous transient voltages. Nevertheless, these two resis-
tors will cause power loss in the RAUX power mode, and
they also reduce the effective RAUX input voltage level
sensed by the VIN pin of the LM5072. The resistors should
be made as large as is practical for the application. But, with
a low RAUX input voltage (
be reduced to a lower value.
During RAUX operation, the hot swap MOSFET is turned off.
Consequently, the substrate of the IC no longer has a low
impedance path to power return. It is advised that the user
remove C27 and populate C29. A capacitor across the hot
swap MOSFET will act as both the signature capacitor and a
high frequency short for any substrate noise.
If the RAUX power option is not used in a new design, delete
C3, D1, D2, R1, R2, R13, R29 and J3 from the circuit to
lower the BOM cost.
Auxiliary Dominant in RAUX Power
Option
The evaluation board is populated for auxiliary dominance in
the RAUX power option. This is achieved by selecting 4.99
kΩ for R13. In applications where auxiliary dominance is not
desirable, change the installed R13 to a higher value. Please
refer to the LM5072 datasheet for assistance in selecting this
value.
Auxiliary Input “OR-ing” Diode
Selection
Special attention should be paid to the selection of D1 and
D3. They need not be high speed diodes because there is no
switching action during operation associated with these com-
ponents, but they should be low reverse leakage current
devices. Otherwise, the leakage current during operation
may create a false signal at the ICL_FAUX pin, the RAUX
pin, or both, as if the circuit is powered from the FAUX or
RAUX source. Leakage current into the ICL_FAUX pin may
also corrupt inrush current programming, if implemented.
Most diode and transistor datasheets provide information on
the maximum leakage current at both 25˚C and 125˚C,
although the data for the intermediate temperatures are not
often supplied. It can be approximated that the leakage
current doubles for every 10˚C rise in temperature.
The junction temperature of these devices should not reach
125˚C because the only dissipation inside these devices is
caused by the leakage current. Therefore, it is not necessary
to select the devices based on the maximum leakage current
specified at 125˚C. The evaluation board design considered
55˚C as the maximum junction temperature of these de-
vices, which is acceptable for most PoE applications. Simple
circuit adjustments can be made if higher leakage currents
are expected.
Resistors R29 and C1 (note that a resistor is installed at the
C1 loacation on the evaluation board to achieve the function
similar to R29’s) are both 24.9 kΩ, providing paths for the
leakage currents of D1 and D3, respectively. These two
resistors are meant to sink all of the leakage current from the
<
16V), R1 and R2 may need to
www.national.com