ISL8104EVAL1Z Intersil, ISL8104EVAL1Z Datasheet - Page 9

• Manufacturer Part Number: ISL8104EVAL1Z
• Description: EVALUATION BOARD FOR ISL8104
• Manufacturer: Intersil

Specifications of ISL8104EVAL1Z

• Main Purpose: DC/DC, Step Down
• Outputs And Type: 1, Non-Isolated
• Voltage - Output: 1.8V
• Current - Output: 20A
• Voltage - Input: 8 ~ 14.4V
• Regulator Topology: Buck
• Frequency - Switching: 300kHz
• Board Type: Fully Populated
• Utilized Ic / Part: ISL8104
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Power - Output: -

The power plane should support the input power and output
power nodes. Use copper filled polygons on the top and
bottom circuit layers for the LX nodes. Use the remaining
printed circuit layers for small signal wiring.
Locate the ISL8104 within 2 to 3 inches of the MOSFETs, Q
and Q
circuit traces for the MOSFETs’ gate and source connections
from the ISL8104 must be sized to handle up to 3A peak
current. Minimize any leakage current paths on the SS pin and
locate the capacitor, C
current source is only 30µA. Provide local V
between VCC and GND pins. Locate the capacitor, C
close as practical to the BOOT pin and the phase node.
Compensating the Converter
This section highlights the design consideration for a voltage
mode controller requiring external compensation. To address a
broad range of applications, a type-3 feedback network is
recommended (see Figure 6).
FIGURE 7. VOLTAGE-MODE BUCK CONVERTER
FIGURE 6. COMPENSATION CONFIGURATION FOR THE
2
(1 inch or less for 500kHz or higher operation). The
CIRCUIT
C
R
PWM
3
3
COMP
COMPENSATION DESIGN
ISL8104 CIRCUIT
HALF-BRIDGE
OSCILLATOR
V
DRIVE
OSC
R
E/A
ss
R
1
2
R
ISL8104
close to the SS pin as the internal
VOUT
2
C
C
+
VREF
-
2
2
C
C
9
1
1
FB
TGATE
BGATE
LX
EXTERNAL CIRCUIT
GND
COMP
FB
R
3
V
IN
R
CC
1
C
L
3
decoupling
ISL8104
DCR
V
ESR
OUT
C
BOOT
as
1
ISL8104
Figure 7 highlights the voltage-mode control loop for a
synchronous-rectified buck converter. The output voltage is
regulated to the reference voltage level. The error amplifier
output is compared with the oscillator triangle wave to
provide a pulse-width modulated wave with an amplitude of
V
output filter. The output filter capacitor bank’s equivalent
series resistance is represented by the series resistor ESR.
The modulator transfer function is the small-signal transfer
function of V
DC gain and shaped by the output filter, with a double pole
break frequency at F
of this analysis, L and DCR represent the output inductance
and its DCR, while C and ESR represents the total output
capacitance and its equivalent series resistance.
The compensation network consists of the error amplifier
(internal to the ISL8104) and the external R
components. The goal of the compensation network is to
provide a closed loop transfer function with high 0dB crossing
frequency (F
margin (better than 45°). Phase margin is the difference
between the closed loop phase at F
equations that follow relate the compensation network’s poles,
zeros and gain to the components (R
C
locating the poles and zeros of the compensation network:
F
1. Select a value for R
2. Calculate C
3. Calculate C
4. Calculate R
IN
LC
3
) in Figures 6 and 7. Use the following guidelines for
value for R
setting the output voltage to be equal to the reference set
voltage as shown in Figure 7, the design procedure can
be followed as presented in Equation 8.
As the ISL8104 supports 100% duty cycle, D
The ISL8104 uses a fixed ramp amplitude (V
Equation 8 simplifies to Equation 9:
at 0.1 to 0.75 of F
Equation 10 to the desired number). The higher the quality
factor of the output filter and/or the higher the ratio
F
phase boost at F
such that F
C
C
at the LX node. The PWM wave is smoothed by the
R
R
=
CE
1
2
2
2
---------------------------
2π
=
=
=
=
/F
---------------------------------------------- -
2π R
------------------------------------------------------- -
2π R
⋅
--------------------------------------------- -
D
1.9 R
------------------------------ -
LC
1
V
V
MAX
L C
0
OSC
IN
OUT
⋅
⋅
, the lower the F
; typically 0.1 to 0.3 of f
⋅
⋅
2
⋅
1
2
2
2
P2
3
⋅
1
F
such that F
⋅
⋅
for desired converter bandwidth (F
V
such that F
/V
⋅
such that F
1
LC
⋅
0.5 F
C
C
R
is placed below f
IN
F
COMP
1
1
1
0
⋅
LC
⋅
LC
LC
⋅
⋅
F
F
F
CE
LC
0
LC
).
1
(to adjust, change the 0.5 factor in
and a zero at F
F
. This function is dominated by a
(1kΩ to 10kΩ, typically). Calculate
CE
–
Z1
P1
1
Z2
Z1
=
is placed at a fraction of the F
is placed at F
is placed at F
-------------------------------- -
2π C ESR
frequency (to maximize
⋅
0dB
SW
SW
1
1
⋅
, R
) and adequate phase
(typically, 0.3 to 1.0
and 180°. The
CE
2
, R
. For the purpose
1
CE
LC
to R
3
, C
.
. Calculate C
MAX
OSC
3
1
, C
, C
March 7, 2008
0
equals 1.
) of 1.9V,
1
). If
(EQ. 11)
(EQ. 10)
2
(EQ. 7)
(EQ. 8)
(EQ. 9)
FN9257.2
to C
, and
LC
3
3
,