ISL8104EVAL1Z Intersil, ISL8104EVAL1Z Datasheet - Page 8

• Manufacturer Part Number: ISL8104EVAL1Z
• Description: EVALUATION BOARD FOR ISL8104
• Manufacturer: Intersil

Specifications of ISL8104EVAL1Z

• Main Purpose: DC/DC, Step Down
• Outputs And Type: 1, Non-Isolated
• Voltage - Output: 1.8V
• Current - Output: 20A
• Voltage - Input: 8 ~ 14.4V
• Regulator Topology: Buck
• Frequency - Switching: 300kHz
• Board Type: Fully Populated
• Utilized Ic / Part: ISL8104
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Power - Output: -

will repeat this process in a hiccup mode. Figure 4 shows a
typical reaction to a repeated overcurrent condition that
places the regulator in a hiccup mode. If the regulator is
repeatedly tripping overcurrent, the hiccup period can be
approximated by Equation 5:
The OCP trip point varies mainly due to MOSFET r
variations and layout noise concerns. To avoid overcurrent
tripping in the normal operating load range, find the R
resistor from the following equations with:
Determine the overcurrent trip point greater than the
maximum output continuous current at maximum inductor
ripple current.
High Speed MOSFET Gate Driver
The integrated driver has the same drive capability and
feature as the Intersil’s 12V gate driver, ISL6612. The PWM
tri-state feature helps prevent a negative transient on the
output voltage when the output is being shut down. This
eliminates the Schottky diode that is used in some systems
for protecting the loads from reversed-output-voltage
damage. See the ISL6612 data sheet FN9153 for
specification parameters that are not defined in the current
ISL8104 “Electrical Specifications” table on page 4.
Reference Input
The REFIN pin allows the user to bypass the internal 0.597V
reference with an external reference. If REFIN is NOT above
~2.2V, the external reference pin is used as the control
reference instead of the internal 0.597V reference. When not
using the external reference option, the REFIN pin should be
left floating. An internal 6µA pull-up keeps this REFIN pin
above 2.2V in this situation.
Internal Reference and System Accuracy
The Internal Reference is set to 0.597V. The total DC system
accuracy of the system is to be within 1.5% over the industrial
t
HICCUP
1. The maximum r
2. The minimum I
temperature
=
N
R
2 4V C
------------------------------- -
T
f
TSOC
⋅
SW
30μA
R
=
DETAILED OCP EQUATION
TSOC
NUMBER OF TOP-SIDE MOSFETs
SIMPLE OCP EQUATION
⋅
=
ΔI =
TSOC
=
Regulator Switching Frequency
DS(ON)
SS
⎛
⎝
--------------------------------------------------------------------------------- -
=
I
OC_SOURCE
V
------------------------------- -
f
SW
I
--------------------------------------------------------------- -
IN
OC_SOURCE
from the specification table
- V
•
at the highest junction
L
OUT
I
OUT
8
TSOC
200μA
•
+
V
--------------- -
•
I Δ
---- -
r •
2
V
OUT
N
⎞
⎠
IN
DS ON
T
r •
(
DS ON
(
)
)
DS(ON)
OCSET
(EQ. 6)
(EQ. 5)
ISL8104
temperature range. System Accuracy includes Error Amplifier
offset, and Reference Error. The use of REFIN may add up to
3mV of offset error into the system (as the Error Amplifier
offset is trimmed out via the internal System reference).
Application Guidelines
Layout Considerations
As in any high frequency switching converter, layout is very
important. Switching current from one power device to another
can generate voltage transients across the impedances of the
interconnecting bond wires and circuit traces. These
interconnecting impedances should be minimized by using
wide, short printed circuit traces. The critical components
should be located as close together as possible using ground
plane construction or single point grounding.
A multi-layer printed circuit board is recommended. Figure 5
shows the critical components of the converter. Note that
capacitors C
physical capacitors. Dedicate one solid layer (usually a middle
layer of the PC board) for a ground plane and make all critical
component ground connections with vias to this layer.
Dedicate another solid layer as a power plane and break this
plane into smaller islands of common voltage levels. Keep the
metal runs from the LX terminals to the output inductor short.
FIGURE 5. PRINTED CIRCUIT BOARD POWER PLANES
KEY
GND
ISL8104
VIA CONNECTION TO GROUND PLANE
TRACE SIZED FOR 3A PEAK CURRENT
SHORT TRACE, MINIMUM IMPEDANCE
ISLAND ON POWER PLANE LAYER
ISLAND ON CIRCUIT AND/OR POWER PLANE LAYER
IN
BGATE
TGATE
PGND
AND ISLANDS
BOOT
PVCC
and C
VCC
SS
LX
OUT
C
C
C
could each represent numerous
BP_PVCC
BP_VCC
SS
+14V
C
IN
Q
Q
1
2
L
VIN
OUT
C
C
OUT
IN
V
OUT
March 7, 2008
FN9257.2