ADC08D1020DEV/NOPB National Semiconductor, ADC08D1020DEV/NOPB Datasheet - Page 38

• Manufacturer Part Number: ADC08D1020DEV/NOPB
• Description: BOARD DEV FOR ADC08D1020
• Manufacturer: National Semiconductor
• Series: PowerWise®r

Specifications of ADC08D1020DEV/NOPB

• Number Of Adc's: 2
• Number Of Bits: 8
• Sampling Rate (per Second): 1G
• Data Interface: Serial
• Inputs Per Adc: 1 Differential
• Input Range: 870 mVpp
• Power (typ) @ Conditions: 1.6W @ 1GSPS
• Voltage Supply Source: Single Supply
• Operating Temperature: -40°C ~ 85°C
• Utilized Ic / Part: ADC08D1020
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: ADC08D1020DEV

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outputs are continuously present at the output only when the
Resistor Trim Disable is active.
2.4.2.1 Power-On Calibration
Power-on calibration begins after a time delay following the
application of power. This time delay is determined by the
setting of CalDly, as described in the Calibration Delay Sec-
tion, below.
The calibration process will be not be performed if the CAL
pin is high at power up. In this case, the calibration cycle will
not begin until the on-command calibration conditions are
met. The ADC08D1020 will function with the CAL pin held
high at power up, but no calibration will be done and perfor-
mance will be impaired. A manual calibration, however, may
be performed after powering up with the CAL pin high. See
On-Command Calibration
The internal power-on calibration circuitry comes up in an un-
known logic state. If the input clock is not running at power up
and the power on calibration circuitry is active, it will hold the
analog circuitry in power down and the power consumption
will typically be less than 200 mW. The power consumption
will be normal after the clock starts.
2.4.2.2 On-Command Calibration
To initiate an on-command calibration, bring the CAL pin high
for a minimum of t
low for a minimum of t
CAL pin high upon power up will prevent execution of power-
on calibration until the CAL pin is low for a minimum of
t
another t
begin t
brought high. The CalRun signal should be monitored to de-
termine when the calibration cycle has completed.
The minimum t
required to ensure that random noise does not cause a cali-
bration to begin when it is not desired. As mentioned for best
performance, a calibration should be performed 20 seconds
or more after power up and repeated when the operating
temperature changes significantly relative to the specific sys-
tem design performance requirements.
By default, On-Command calibration also includes calibrating
the input termination resistance and the ADC. However, since
the input termination resistance, once trimmed at power-up,
changes marginally with temperature, the user has the option
to disable the input termination resistor trim, which will guar-
antee that the DCLK is continuously present at the output
during subsequent calibration. The Resistor Trim Disable can
be programmed in register (address: 1h, bit 13) when in the
Extended Control mode. Refer to for register programming
information.
2.4.2.3 Calibration Delay
The CalDly input (pin 127) is used to select one of two delay
times after the application of power to the start of calibration,
as described in
allow the power supply to come up and stabilize before cali-
bration takes place. With no delay or insufficient delay, cali-
bration would begin before the power supply is stabilized at
its operating value and result in non-optimal calibration coef-
ficients. If the PD pin is high upon power-up, the calibration
delay counter will be disabled until the PD pin is brought low.
Therefore, holding the PD pin high during power up will further
delay the start of the power-up calibration cycle. The best
setting of the CalDly pin depends upon the power-on settling
time of the power supply.
CAL_L
input clock cycles, then brought high for a minimum of
CAL_H
CAL_H
input clock cycles after the CAL pin is thus
CAL_L
input clock cycles. The calibration cycle will
1.1.1
CAL_H
and t
Calibration. The calibration delay values
CAL_L
input clock cycles after it has been
CAL_H
2.4.2.2 On-Command
input clock cycles. Holding the
input clock cycle sequence is
Calibration.
38
Note that the calibration delay selection is not possible in the
Extended Control mode and the short delay time is used.
2.4.3 Output Edge Synchronization
DCLK signals are available to help latch the converter output
data into external circuitry. The output data can be synchro-
nized with either edge of these DCLK signals. That is, the
output data transition can be set to occur with either the rising
edge or the falling edge of the DCLK signal, so that either
edge of that DCLK signal can be used to latch the output data
into the receiving circuit.
When OutEdge (pin 4) is high, the output data is synchronized
with (changes with) the rising edge of the DCLK+ (pin 82).
When OutEdge is low, the output data is synchronized with
the falling edge of DCLK+.
At the very high speeds of which the ADC08D1020 is capable,
slight differences in the lengths of the DCLK and data lines
can mean the difference between successful and erroneous
data capture. The OutEdge pin is used to capture data on the
DCLK edge that best suits the application circuit and layout.
Reliable data capture can be achieved by using just one
DCLK+/- signal for the full 32 signal data bus. However, if de-
sired, the user may configure the OR+/- output as the second
DCLK+/- output instead.
2.4.4 LVDS Output Level Control
The output level can be set to one of two levels with OutV (pin
3). The strength of the output drivers is greater with OutV high.
With OutV low there is less power consumption in the output
drivers, but the lower output level means decreased noise
immunity.
For short LVDS lines and low noise systems, satisfactory per-
formance may be realized with the OutV input low. If the LVDS
lines are long and/or the system in which the ADC08D1020
is used is noisy, it may be necessary to tie the OutV pin high.
2.4.5 Dual Edge Sampling
The Dual Edge Sampling (DES) feature causes one of the two
input pairs to be routed to both ADCs. The other input pair is
deactivated. One of the ADCs samples the input signal on one
input clock edge (duty cycle corrected), the other samples the
input signal on the other input clock edge (duty cycle correct-
ed). If the device is in the 1:2 output demultiplex mode, the
result is an output data rate 1/4 that of the interleaved sample
rate which is twice the input clock frequency. Data is present-
ed in parallel on all four output buses in the following order:
DQd, DId, DQ, DI. If the device is the non-demultiplex output
mode, the result is an output data rate 1/2 that of the inter-
leaved sample rate. Data is presented in parallel on two
output buses in the following order: DQ, DI.
To use this feature in the non-extended control mode, allow
pin 127 to float and the signal at the "I" channel input will be
sampled by both converters. The Calibration Delay will then
only be a short delay.
In the extended control mode, either input may be used for
dual edge sampling. See
2.4.6 Power Down Feature
The Power Down pins (PD and PDQ) allow the ADC08D1020
to be entirely powered down (PD) or the "Q" channel to be
powered down and the "I" channel to remain active. See
Power Down
The digital data (+/-) output pins are put into a high impedance
state when the PD pin for the respective channel is high. Upon
return to normal operation, the pipeline will contain meaning-
less information and must be flushed.
for details on the power down feature.
1.1.5.1 Dual-Edge
Sampling.
1.1.7