ADC08D1020DEV/NOPB National Semiconductor, ADC08D1020DEV/NOPB Datasheet - Page 30

• Manufacturer Part Number: ADC08D1020DEV/NOPB
• Description: BOARD DEV FOR ADC08D1020
• Manufacturer: National Semiconductor
• Series: PowerWise®r

Specifications of ADC08D1020DEV/NOPB

• Number Of Adc's: 2
• Number Of Bits: 8
• Sampling Rate (per Second): 1G
• Data Interface: Serial
• Inputs Per Adc: 1 Differential
• Input Range: 870 mVpp
• Power (typ) @ Conditions: 1.6W @ 1GSPS
• Voltage Supply Source: Single Supply
• Operating Temperature: -40°C ~ 85°C
• Utilized Ic / Part: ADC08D1020
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: ADC08D1020DEV

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The default state of the Extended Control Mode is set upon
power-on reset (internally performed by the device) and is
shown in
1.3 THE SERIAL INTERFACE
IMPORTANT NOTE: During the initial write using the serial
interface, all nine registers must be written with desired or
default values. Subsequent writes to single registers are al-
lowed.
The 3-pin serial interface is enabled only when the device is
in the Extended Control mode. The pins of this interface are
Serial Clock (SCLK), Serial Data (SDATA) and Serial Inter-
face Chip Select (SCS). Nine write only registers are acces-
sible through this serial interface.
SCS: This signal should be asserted low while accessing a
register through the serial interface. Setup and hold times with
respect to the SCLK must be observed.
SCLK: Serial data input is accepted at the rising edge of this
signal. There is no minimum frequency requirement for SCLK.
SDATA: Each register access requires a specific 32-bit pat-
tern at this input. This pattern consists of a header, register
address and register value. The data is shifted in MSB first.
Setup and hold times with respect to the SCLK must be ob-
served. See the Timing Diagram.
Each Register access consists of 32 bits, as shown in
6
0000 0001 (eleven zeros followed by a 1). The loading se-
quence is such that a "0" is loaded first. These 12 bits form
the header. The next 4 bits are the address of the register that
is to be written to and the last 16 bits are the data written to
the addressed register. The addresses of the various regis-
ters are indicated in
Refer to the Register Description
TION) for information on the data to be written to the registers.
Subsequent register accesses may be performed immediate-
ly, starting with the 33rd SCLK. This means that the SCS input
does not have to be de-asserted and asserted again between
register addresses. It is possible, although not recommended,
to keep the SCS input permanently enabled (at a logic low)
when using extended control.
Control register contents are retained when the device is put
into power-down mode.
of the Timing Diagrams. The fixed header pattern is 0000
Table
Selectable Output Demultiplexer
Sampling Clock Phase Adjust
Dual Edge Sampling (DES)
4.
LVDS Output Amplitude
SDR or DDR Clocking
Resistor Trim Disable
Second DCLK Output
Input Offset Adjust
DDR Clock Phase
TABLE 4. Extended Control Mode Operation (Pin 41 Logic Low or Pin 14 Floating)
Calibration Delay
Full-Scale Range
Table
Test Pattern
Feature
5.
(1.4 REGISTER DESCRIP-
Figure
30
Trim enabled, DCLK not continuously present at output
No adjustment for fine, intermediate or coarse
IMPORTANT NOTE: Do not write to the Serial Interface when
calibrating the ADC. Doing so will impair the performance of
the device until it is re-calibrated correctly. Programming the
serial registers will also reduce dynamic performance of the
ADC for the duration of the register access time.
Data changes with DCLK edge (0° phase)
Higher value indicated in Electrical Table
Extended Control Mode Default State
A3 loaded after Fixed Header pattern, A0 loaded last
A3 A2 A1
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
700 mV nominal for both channels
No adjustment for either channel
Not present, pins 79 and 80
function as OR+ and OR-
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
Not present at output
TABLE 5. Register Addresses
1:2 demultiplex
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
DDR Clocking
Not enabled
Short Delay
A0 Hex
Loading Sequence:
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
4-Bit Address
Ch
Dh
0h
1h
2h
3h
4h
5h
6h
7h
8h
9h
Ah
Bh
Eh
Fh
"Q" Ch Full-Scale Voltage
"I" Ch Full-Scale Voltage
Intermediate and Coarse
Extended Configuration
Sampling Clock Phase
Register Addressed
Sample Clock Phase
"Q" Ch Offset
Configuration
"I" Ch Offset
Fine Adjust
Calibration
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Adjust
Adjust
Adjust