ADC128S102EVAL/NOPB National Semiconductor, ADC128S102EVAL/NOPB Datasheet - Page 14

• Manufacturer Part Number: ADC128S102EVAL/NOPB
• Description: BOARD EVALUATION FOR ADC128S102
• Manufacturer: National Semiconductor
• Series: PowerWise®r

Specifications of ADC128S102EVAL/NOPB

• Number Of Adc's: 1
• Number Of Bits: 12
• Sampling Rate (per Second): 1M
• Data Interface: Serial
• Inputs Per Adc: 8 Single Ended
• Input Range: 0 ~ 5.25 V
• Power (typ) @ Conditions: 10.7mW @ 1MSPS
• Voltage Supply Source: Analog and Digital
• Operating Temperature: -40°C ~ 105°C
• Utilized Ic / Part: ADC128S102
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: ADC128S102EVAL

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1.0 Functional Description
The ADC128S102 is a successive-approximation analog-to-
digital converter designed around a charge-redistribution dig-
ital-to-analog converter.
1.1 ADC128S102 OPERATION
Simplified schematics of the ADC128S102 in both track and
hold operation are shown in
tively. In
SW1 connects the sampling capacitor to one of eight analog
input channels through the multiplexer, and SW2 balances
the comparator inputs. The ADC128S102 is in this state for
the first three SCLK cycles after CS is brought low.
1.2 SERIAL INTERFACE
An operational timing diagram and a serial interface timing
diagram for the ADC128S102 are shown in The Timing Dia-
grams section. CS, chip select, initiates conversions and
frames the serial data transfers. SCLK (serial clock) controls
both the conversion process and the timing of serial data.
DOUT is the serial data output pin, where a conversion result
is sent as a serial data stream, MSB first. Data to be written
to the ADC128S102's Control Register is placed on DIN, the
serial data input pin. New data is written to DIN with each
conversion.
A serial frame is initiated on the falling edge of CS and ends
on the rising edge of CS. Each frame must contain an integer
multiple of 16 rising SCLK edges. The ADC's DOUT pin is in
a high impedance state when CS is high and is active when
Figure
4, the ADC128S102 is in track mode: switch
Figure 4
and
Figure 5
FIGURE 4. ADC128S102 in Track Mode
FIGURE 5. ADC128S102 in Hold Mode
respec-
14
Figure 5
connects the sampling capacitor to ground, maintaining the
sampled voltage, and switch SW2 unbalances the compara-
tor. The control logic then instructs the charge-redistribution
DAC to add or subtract fixed amounts of charge to or from the
sampling capacitor until the comparator is balanced. When
the comparator is balanced, the digital word supplied to the
DAC is the digital representation of the analog input voltage.
The ADC128S102 is in this state for the last thirteen SCLK
cycles after CS is brought low.
CS is low. Thus, CS acts as an output enable. Similarly, SCLK
is internally gated off when CS is brought high.
During the first 3 cycles of SCLK, the ADC is in the track
mode, acquiring the input voltage. For the next 13 SCLK cy-
cles the conversion is accomplished and the data is clocked
out. SCLK falling edges 1 through 4 clock out leading zeros
while falling edges 5 through 16 clock out the conversion re-
sult, MSB first. If there is more than one conversion in a frame
(continuous conversion mode), the ADC will re-enter the track
mode on the falling edge of SCLK after the N*16th rising edge
of SCLK and re-enter the hold/convert mode on the N*16+4th
falling edge of SCLK. "N" is an integer value.
The ADC128S102 enters track mode under three different
conditions. In
ADC enters track mode on the first falling edge of SCLK. In
the second condition, CS goes low with SCLK low. Under this
shows the ADC128S102 in hold mode: switch SW1
Figure
1, CS goes low with SCLK high and the
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