ADC124S101EVAL National Semiconductor, ADC124S101EVAL Datasheet - Page 17

• Manufacturer Part Number: ADC124S101EVAL
• Description: BOARD EVALUATION FOR ADC124S101
• Manufacturer: National Semiconductor
• Series: PowerWise®r

Specifications of ADC124S101EVAL

• Number Of Adc's: 1
• Number Of Bits: 12
• Sampling Rate (per Second): 1M
• Data Interface: Serial
• Inputs Per Adc: 4 Single Ended
• Input Range: 0 ~ 5.25 V
• Power (typ) @ Conditions: 13.1mW @ 1MSPS
• Voltage Supply Source: Single Supply
• Operating Temperature: -40°C ~ 85°C
• Utilized Ic / Part: ADC124S101
• Lead Free Status / RoHS Status: Not applicable / Not applicable

4.0 TYPICAL APPLICATION CIRCUIT
A typical application of the ADC124S101 is shown in
4. Power is provided in this example by the National Semi-
conductor LP2950 low-dropout voltage regulator, available in
a variety of fixed and adjustable output voltages. The power
supply pin is bypassed with a capacitor network located close
to the ADC124S101.
Because the reference for the ADC124S101 is the supply
voltage, any noise on the supply will degrade device noise
5.0 ANALOG INPUTS
An equivalent circuit for one of the ADC124S101's input chan-
nels is shown in
protection for the analog inputs. At no time should any input
go beyond (V
diodes will begin conducting, which could result in erratic op-
eration. For this reason, these ESD diodes should NOT be
used to clamp the input signal.
The capacitor C1 in
is mainly the package pin capacitance. Resistor R1 is the on
resistance of the multiplexer and track / hold switch, and is
typically 500 ohms. Capacitor C2 is the ADC124S101 sam-
pling capacitor, and is typically 30 pF. The ADC124S101 will
deliver best performance when driven by a low-impedance
source to eliminate distortion caused by the charging of the
sampling capacitance. This is especially important when us-
ing the ADC124S101 to sample AC signals. Also important
when sampling dynamic signals is a band-pass or low-pass
filter to reduce harmonics and noise, improving dynamic per-
formance.
FIGURE 5. Equivalent Input Circuit
A
+ 300 mV) or (GND − 300 mV), as these ESD
Figure
Figure 5
5. Diodes D1 and D2 provide ESD
has a typical value of 3 pF, and
FIGURE 4. Typical Application Circuit
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Figure
17
performance. To keep noise off the supply, use a dedicated
linear regulator for this device, or provide sufficient decou-
pling from other circuitry to keep noise off the ADC124S101
supply pin. Because of the ADC124S101's low power re-
quirements, it is also possible to use a precision reference as
a power supply to maximize performance. The four-wire in-
terface is also shown connected to a microprocessor or DSP.
6.0 DIGITAL INPUTS AND OUTPUTS
The ADC124S101's digital output DOUT is limited by, and
cannot exceed, the supply voltage, V
are not prone to latch-up and, and although not recommend-
ed, SCLK, CS and DIN may be asserted before V
any latch-up risk.
7.0 POWER SUPPLY CONSIDERATIONS
The ADC124S101 is fully powered-up whenever CS is low,
and fully powered-down whenever CS is high, with one ex-
ception: the ADC124S101 automatically enters power-down
mode between the 16th falling edge of a conversion and the
1st falling edge of the subsequent conversion (see Timing
Diagrams).
The ADC124S101 can perform multiple conversions back to
back; each conversion requires 16 SCLK cycles. The AD-
C124S101 will perform conversions continuously as long as
CS is held low.
The user may trade off throughput for power consumption by
simply performing fewer conversions per unit time. The Power
Consumption vs. Sample Rate curve in the Typical Perfor-
mance Curves section shows the typical power consumption
of the ADC124S101 versus throughput. To calculate the pow-
er consumption, simply multiply the fraction of time spent in
the normal mode by the normal mode power consumption,
and add the fraction of time spent in shutdown mode multi-
plied by the shutdown mode power dissipation.
7.1 Power Management
When the ADC124S101 is operated continuously in normal
mode, the maximum throughput is f
be traded for power consumption by running f
imum 16 MHz and performing fewer conversions per unit
time, putting the ADC124S101 into shutdown mode between
conversions. A plot of typical power consumption versus
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SCLK
A
. The digital input pins
/16. Throughput may
SCLK
www.national.com
at its max-
A
without