ADC124S101EVAL National Semiconductor, ADC124S101EVAL Datasheet - Page 16

• Manufacturer Part Number: ADC124S101EVAL
• Description: BOARD EVALUATION FOR ADC124S101
• Manufacturer: National Semiconductor
• Series: PowerWise®r

Specifications of ADC124S101EVAL

• Number Of Adc's: 1
• Number Of Bits: 12
• Sampling Rate (per Second): 1M
• Data Interface: Serial
• Inputs Per Adc: 4 Single Ended
• Input Range: 0 ~ 5.25 V
• Power (typ) @ Conditions: 13.1mW @ 1MSPS
• Voltage Supply Source: Single Supply
• Operating Temperature: -40°C ~ 85°C
• Utilized Ic / Part: ADC124S101
• Lead Free Status / RoHS Status: Not applicable / Not applicable

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During each conversion, data is clocked into the DIN pin on
the first 8 rising edges of SCLK after the fall of CS. For each
conversion, it is necessary to clock in the data indicating the
input that is selected for the conversion after the current one.
See Tables 1, 2 and
If CS and SCLK go low within the times defined by t
t
DIN may be one clock cycle later than expected. It is, there-
3.0 ADC124S101 TRANSFER FUNCTION
The output format of the ADC124S101 is straight binary.
Code transitions occur midway between successive integer
LSB values. The LSB width for the ADC124S101 is V
CLH
, the rising edge of SCLK that begins clocking data in at
Bit 7 (MSB)
DONTC
7 - 6, 2 - 0
Bit #:
5
4
3
Table
DONTC
3.
Symbol:
Bit 6
DONTC
ADD2
ADD1
ADD0
ADD2
TABLE 2. Control Register Bit Descriptions
Description
Don't care. The value of these bits do not affect device operation.
These three bits determine which input channel will be sampled and converted
in the next track/hold cycle. The mapping between codes and channels is shown
in
x
x
x
x
ADD2
FIGURE 3. Ideal Transfer Characteristic
Bit 5
Table
TABLE 3. Input Channel Selection
TABLE 1. Control Register Bits
3.
ADD1
CSU
A
0
0
1
1
/4096.
ADD1
and
Bit 4
16
ADD0
0
1
0
1
fore, best to strictly observe the minimum t
given in the Timing Specifications..
There are no power-up delays or dummy conversions re-
quired with the ADC124S101. The ADC is able to sample and
convert an input to full conversion immediately following pow-
er up. The first conversion result after power-up will be that of
IN1.
The ideal transfer characteristic is shown in
transition from an output code of 0000 0000 0000 to a code
of 0000 0000 0001 is at 1/2 LSB, or a voltage of V
Other code transitions occur at steps of one LSB.
ADD0
Bit 3
Input Channel
IN1 (Default)
IN2
IN3
IN4
DONTC
Bit 2
20124911
DONTC
Bit 1
CSU
and t
Figure
DONTC
Bit 0
CLH
A
3. The
/8192.
times