AD13280/PCB Analog Devices Inc, AD13280/PCB Datasheet - Page 17

• Manufacturer Part Number: AD13280/PCB
• Description: KIT EVAL PCB FOR AD13280
• Manufacturer: Analog Devices Inc

Specifications of AD13280/PCB

• Rohs Status: RoHS non-compliant
• Number Of Adc's: 2
• Number Of Bits: 12
• Sampling Rate (per Second): 80M
• Data Interface: Parallel
• Inputs Per Adc: 1 Differential
• Input Range: ±1 V
• Power (typ) @ Conditions: 3.7W @ 80MSPS
• Voltage Supply Source: Analog and Digital, Dual ±
• Operating Temperature: -25°C ~ 85°C
• Utilized Ic / Part: AD13280

EVALUATION BOARD
The AD13280 evaluation board (see Figure 20) is designed to
provide optimal performance for evaluation of the AD13280
analog-to-digital converter. The board encompasses everything
needed to ensure the highest level of performance for evaluating
the AD13280. The board requires an analog input signal, encode
clock, and power supply inputs. The clock is buffered on-board
to provide clocks for the latches. The digital outputs and out
clocks are available at the standard 40-pin connectors J1 and J2.
Power to the analog supply pins is connected via banana jacks.
The analog supply powers the associated components and the
analog section of the AD13280. The digital outputs of the
AD13280 are powered via banana jacks with 3.3 V. Contact the
factory if additional layout or applications assistance is required.
Figure 20. Evaluation Board Mechanical Layout
Rev. C | Page 17 of 28
LAYOUT INFORMATION
The schematics of the evaluation board (Figure 21, Figure 22,
and Figure 23) represent a typical implementation of the
AD13280. The pinout of the AD13280 is very straightforward
and facilitates ease of use and the implementation of high
frequency/high resolution design practices. It is recommended
that high quality ceramic chip capacitors be used to decouple
each supply pin to ground directly at the device. All capacitors
can be standard, high quality ceramic chip capacitors.
Care should be taken when placing the digital output runs.
Because the digital outputs have such a high slew rate, the
capacitive loading on the digital outputs should be minimized.
Circuit traces for the digital outputs should be kept short and
should connect directly to the receiving gate. Internal circuitry
buffers the outputs of the ADC through a resistor network to
eliminate the need to externally isolate the device from the
receiving gate.
AD13280