AD13280/PCB Analog Devices Inc, AD13280/PCB Datasheet - Page 15

• Manufacturer Part Number: AD13280/PCB
• Description: KIT EVAL PCB FOR AD13280
• Manufacturer: Analog Devices Inc

Specifications of AD13280/PCB

• Rohs Status: RoHS non-compliant
• Number Of Adc's: 2
• Number Of Bits: 12
• Sampling Rate (per Second): 80M
• Data Interface: Parallel
• Inputs Per Adc: 1 Differential
• Input Range: ±1 V
• Power (typ) @ Conditions: 3.7W @ 80MSPS
• Voltage Supply Source: Analog and Digital, Dual ±
• Operating Temperature: -25°C ~ 85°C
• Utilized Ic / Part: AD13280

APPLICATIONS INFORMATION
ENCODING THE AD13280
The AD13280 encode signal must be a high quality, extremely
low phase noise source to prevent degradation of performance.
Maintaining 12-bit accuracy at 80 MSPS places a premium on
encode clock phase noise. SNR performance can easily degrade
3 dB to 4 dB with 37 MHz input signals when using a high jitter
clock source. See Analog Devices Application Note AN-501,
Aperture Uncertainty and ADC System Performance, for com-
plete details. For optimum performance, the AD13280 must be
clocked differentially. The encode signal is usually ac-coupled
into the ENCODE and ENCODE pins via a transformer or
capacitors. These pins are biased internally and require no
additional bias.
Figure 17 shows one preferred method for clocking the AD13280.
The clock source (low jitter) is converted from single-ended to
differential using an RF transformer. The back-to-back Schottky
diodes across the transformer secondary limit clock excursions
into the AD13280 to approximately 0.8 V p-p differential. This
helps prevent the large voltage swings of the clock from feeding
through to the other portions of the AD13280 and limits the
noise presented to the ENCODE inputs. A crystal clock
oscillator can also be used to drive the RF transformer if an
appropriate limited resistor (typically 100 Ω) is placed in series
with the primary.
If a low jitter ECL/PECL clock is available, another option is to
ac-couple a differential ECL/PECL signal to the encode input
pins as shown below. A device that offers excellent jitter per-
formance is the MC100LVEL16 (or within the same family)
from Motorola.
SOURCE
ECL/PECL
CLOCK
Figure 17. Crystal Clock Oscillator—Differential Encode
Figure 18. Differential ECL for Encode
0.1µF
100
Ω
VT
VT
T1-4T
HSMS2812
0.1 µF
0.1µF
DIODES
ENCODE
ENCODE
ENCODE
ENCODE
AD13280
AD13280
Rev. C | Page 15 of 28
JITTER CONSIDERATION
The signal-to-noise ratio for any ADC can be predicted. When
normalized to ADC codes, Equation 1 accurately predicts the
SNR based on three terms. These are jitter, average DNL error,
and thermal noise. Each of these terms contributes to the noise
within the converter.
where:
f
t
and internal encode circuitry).
ε is the average DNL of the ADC (typically 0.50 LSB).
N is the number of bits in the ADC.
V
For a 12-bit analog-to-digital converter like the AD13280,
aperture jitter can greatly affect the SNR performance as the
analog frequency is increased. The chart below shows a family
of curves that demonstrates the expected SNR performance of
the AD13280 as jitter increases. The chart is derived from
Equation 1.
For a complete discussion of aperture jitter, consult Analog
Devices Application Note AN-501, Aperture Uncertainty and
ADC System Performance.
SNR
ANALOG
J rms
NOISE rms
is the rms jitter of the encode (rms sum of encode source
=
−
71
70
69
68
67
66
65
64
63
62
61
60
59
58
is the analog input frequency.
20
is the analog input of the ADC (typically 5 LSB).
×
log
⎡
⎢
⎢
⎣
⎡ +
⎢
⎣
1
2
N
ε
⎤
⎥
⎦
Figure 19. SNR vs. Jitter
2
+
CLOCK JITTER (ps)
(
2
×
π
×
f
ANALOG
×
t
J
rms
A
A
A
A
IN
)
IN
IN
IN
2
= 10MHz
= 20MHz
= 37MHz
+
= 5MHz
⎛
⎜ ⎜
⎝
AD13280
V
NOISE
2
N
rms
⎞
⎟ ⎟
⎠
2
⎤
⎥
⎥
⎦
1
(1)
2 /