CDB5361 Cirrus Logic Inc, CDB5361 Datasheet - Page 17

BOARD EVAL FOR CS5361 STEREO ADC

CDB5361

Manufacturer Part Number
CDB5361
Description
BOARD EVAL FOR CS5361 STEREO ADC
Manufacturer
Cirrus Logic Inc
Datasheets

Specifications of CDB5361

Number Of Adc's
2
Number Of Bits
24
Sampling Rate (per Second)
192k
Data Interface
Serial
Inputs Per Adc
1 Differential
Power (typ) @ Conditions
198mW @ 5 V
Voltage Supply Source
Analog and Digital
Operating Temperature
-10°C ~ 70°C
Utilized Ic / Part
CS5361
Product
Audio Modules
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Lead Free Status / RoHS Status
Lead free / RoHS Compliant, Contains lead / RoHS non-compliant
Other names
598-1547
4.2.2
In Master mode, LRCK and SCLK operate as outputs. The left/right and serial clocks are internally derived from the
master clock with the left/right clock equal to Fs and the serial clock equal to 64x Fs, as shown in Figure 23. Refer
to Table 3 for common master clock frequencies.
DS467F2
MCLK
Master Mode
SAMPLE RATE (kHz)
176.4
÷ 1
÷ 2
44.1
88.2
192
32
48
64
96
Table 3. CS5361 Common Master Clock Frequencies
MDIV
1
0
Figure 23. CS5361 Master Mode Clocking
MCLK (MHz)
MDIV = 0
11.2896
11.2896
11.2896
12.288
12.288
12.288
8.192
8.192
÷ 256
÷ 128
÷ 64
÷ 4
÷ 2
÷ 1
Double
Double
Single
Speed
Speed
Speed
Speed
Speed
Speed
Single
Quad
Quad
MCLK (MHz)
M1
MDIV = 1
00
01
10
22.5792
22.5792
22.5792
00
01
10
16.384
24.576
16.384
24.576
24.576
M0
LRCK Output
(Equal to Fs)
CS5361
SCLK Output
17

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