CDB5381 Cirrus Logic Inc, CDB5381 Datasheet - Page 16

• Manufacturer Part Number: CDB5381
• Description: BOARD EVAL FOR CS5381 192KHZ ADC
• Manufacturer: Cirrus Logic Inc

Specifications of CDB5381

• Number Of Adc's: 2
• Number Of Bits: 24
• Sampling Rate (per Second): 192k
• Data Interface: Serial
• Inputs Per Adc: 1 Differential
• Input Range: 6.1 Vpp
• Power (typ) @ Conditions: 360mW @ 5 V
• Voltage Supply Source: Analog and Digital
• Operating Temperature: -10°C ~ 70°C
• Utilized Ic / Part: CS5381
• Product: Audio Modules
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant, Contains lead / RoHS non-compliant
• Other names: 598-1008

16
3.2.2
3.3
3.4
Power-Up Sequence
Reliable power-up can be accomplished by keeping the device in reset until the power supplies, clocks and
configuration pins are stable. It is also recommended that reset be enabled if the analog or digital supplies
drop below the minimum specified operating voltages to prevent power glitch related issues.
The internal reference voltage must be stable for the device to produce valid data. Therefore, there is a de-
lay between the release of reset and the generation of valid output, due to the finite output impedance of
FILT+ and the presence of the external capacitance. This duration of this delay is less than 2500 LRCK cy-
cles.
Analog Connections
The analog modulator samples the input at 6.144 MHz. The digital filter will reject signals within the stop-
band of the filter. However, there is no rejection for input signals which are (n
band frequency, where n=0,1,2,... Refer to
any noise energy at 6.144 MHz in addition to providing the optimum source impedance for the modulators.
The use of capacitors which have a large voltage coefficient (such as general purpose ceramics) must be
avoided since these can degrade signal linearity. C0G capacitors are recommended for this application.
Slave Mode
LRCK and SCLK operate as inputs in Slave mode. It is recommended that the left/right clock be synchro-
nously derived from the master clock and must be equal to Fs. It is also recommended that the serial clock
be synchronously derived from the master clock and be equal to 64x Fs to maximize system performance.
Refer to
MCLK/LRCK Ratio
SCLK/LRCK Ratio
* Only available in Master mode.
SAMPLE RATE (kHz)
Table 3
176.4
44.1
88.2
192
32
48
64
96
for required clock ratios.
Fs = 2 kHz to 54 kHz
Single-Speed Mode
Table 2. CS5381 Common Master Clock Frequencies
256x, 512x
64x, 128x
Table 3. CS5381 Slave Mode Clock Ratios
MCLK (MHz)
Figure
Fs = 50 kHz to 108 kHz
MDIV = 0
Double-Speed Mode
11.2896
11.2896
11.2896
12.288
12.288
12.288
8.192
8.192
24, which shows the suggested filter that will attenuate
128x, 256x
64x
Fs = 100 kHz to 216 kHz
Quad-Speed Mode
MCLK (MHz)
MDIV = 1
×
22.5792
22.5792
22.5792
16.384
24.576
16.384
24.576
24.576
64x*, 128x
6.144 MHz) the digital pass-
64x
CS5381
DS563F2