EVAL-AD7677CBZ Analog Devices Inc, EVAL-AD7677CBZ Datasheet - Page 18

• Manufacturer Part Number: EVAL-AD7677CBZ
• Description: BOARD EVALUATION FOR AD7677
• Manufacturer: Analog Devices Inc
• Series: PulSAR®r

Specifications of EVAL-AD7677CBZ

• Number Of Adc's: 1
• Number Of Bits: 16
• Sampling Rate (per Second): 1M
• Data Interface: Serial, Parallel
• Inputs Per Adc: 1 Differential
• Input Range: ±VREF
• Power (typ) @ Conditions: 115mW @ 1MSPS
• Voltage Supply Source: Analog and Digital
• Operating Temperature: -40°C ~ 85°C
• Utilized Ic / Part: AD7677
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

AD7677
normally high or normally low when inactive. Figure 19 and
Figure 20 show the detailed timing diagrams of these methods.
While the AD7677 is performing a bit decision, it is important that
voltage transients not occur on digital input/output pins or degra-
dation of the conversion result could occur. This is particularly
important during the second half of the conversion phase because
the AD7677 provides error correction circuitry that can correct for
an improper bit decision made during the first half of the conver-
sion phase. For this reason, it is recommended that when an
external clock is being provided, it is a discontinuous clock that is
toggling only when BUSY is low or, more importantly, that it does
not transition during the latter half of BUSY high.
External Discontinuous Clock Data Read after Conversion
This mode is the most recommended of the serial slave modes.
Figure 19 shows the detailed timing diagrams of this method.
After a conversion is complete, indicated by BUSY returning
low, the result of this conversion can be read while both CS and
RD are low. The data is shifted out, MSB first, with 16 clock
pulses and is valid on both the rising and falling edge of the clock.
Among the advantages of this method, the conversion perfor-
mance is not degraded because there are no voltage transients
on the digital interface during the conversion process.
Another advantage is to be able to read the data at any speed up
to 40 MHz, which accommodates both slow digital host inter-
face and the fastest serial reading.
Finally, in this mode only, the AD7677 provides a “daisy chain”
feature using the RDC/SDIN input pin for cascading multiple
converters together. This feature is useful for reducing compo-
nent count and wiring connections when it is desired as it is, for
instance, in isolated multiconverters applications.
An example of the concatenation of two devices is shown in
Figure 21. Simultaneous sampling is possible by using a common
CNVST signal. It should be noted that the RDC/SDIN input is
latched on the opposite edge of SCLK of the one used to shift
out the data on SDOUT. Hence, the MSB of the “upstream”
converter just follows the LSB of the “downstream” converter
on the next SCLK cycle.
External Clock Data Read During Conversion
Figure 20 shows the detailed timing diagrams of this method.
During a conversion, while both CS and RD are low, the result
of the previous conversion can be read. The data is shifted out,
MSB first, with 16 clock pulses, and is valid on both rising and
falling edges of the clock. The 16 bits have to be read before the
Figure 21. Two AD7677s in a “Daisy Chain” Configuration
CNVST IN
SCLK IN
CS IN
RDC/SDIN
#2 (UPSTREAM)
AD7677
BUSY
SDOUT
CNVST
SCLK
CS
RDC/SDIN
#1 (DOWNSTREAM)
AD7677
BUSY
SDOUT
CNVST
SCLK
CS
BUSY
OUT
DATA
OUT
–18–
current conversion is complete. If that is not done, RDERROR
is pulsed high and can be used to interrupt the host interface
to prevent incomplete data reading. There is no “daisy chain”
feature in this mode, and RDC/SDIN input should always be
tied either high or low.
To reduce performance degradation due to digital activity, a fast
discontinuous clock of at least 25 MHz, when Impulse Mode is
used, 32 MHz when normal, or 40 MHz when Warp Mode is
used, is recommended to ensure that all the bits are read during
the first half of the conversion phase. It is also possible to begin
to read the data after conversion and continue to read the last
bits even after a new conversion has been initiated. That allows
the use of a slower clock speed like 18 MHz in Impulse Mode,
21 MHz in Normal Mode, and 26 MHz in Warp Mode.
MICROPROCESSOR INTERFACING
The AD7677 is ideally suited for traditional dc measurement
applications supporting a microprocessor and ac signal process-
ing applications interfacing to a digital signal processor. The
AD7677 is designed to interface either with a parallel 8-bit or
16-bit wide interface or with a general-purpose serial port or I/O
ports on a microcontroller. A variety of external buffers can be
used with the AD7677 to prevent digital noise from coupling into
the ADC. The following sections illustrate the use of the AD7677
with an SPI equipped microcontroller, the ADSP-21065L and
ADSP-218x signal processors.
SPI Interface (MC68HC11)
Figure 22 shows an interface diagram between the AD7677 and an
SPI-equipped microcontroller like the MC68HC11. To accom-
modate the slower speed of the microcontroller, the AD7677
acts as a slave device and data must be read after conversion. This
mode also allows the “daisy chain” feature. The convert command
could be initiated in response to an internal timer interrupt. The
reading of output data, one byte at a time, if necessary, could be
initiated in response to the end-of-conversion signal (BUSY going
low) using an interrupt line of the microcontroller. The Serial
Peripheral Interface (SPI) on the MC68HC11 is configured for
master mode (MSTR) = 1, Clock Polarity Bit (CPOL) = 0, Clock
Phase Bit (CPHA) = 1, and SPI interrupt enable (SPIE) = 1 by
writing to the SPI Control Register (SPCR). The IRQ is configured
for edge-sensitive-only operation (IRQE = 1 in OPTION Register).
ADSP-21065L in Master Serial Interface
As shown in Figure 23, the AD7677 can be interfaced to the
ADSP-21065L using the serial interface in master mode with-
out any glue logic required. This mode combines the advantages
of reducing the wire connections and the ability to read the data
during or after conversion maximum speed transfer (DIVSCLK
[0:1] both low).
Figure 22. Interfacing the AD7677 to SPI Interface
DVDD
SER/PAR
EXT/INT
CS
RD
INVSCLK
AD7677*
*ADDITIONAL PINS OMITTED FOR CLARITY
SDOUT
CNVST
BUSY
SCLK
IRQ
MISO/SDI
SCK
I/O PORT
MC68HC11*
REV. A