EVAL-AD7654CBZ Analog Devices Inc, EVAL-AD7654CBZ Datasheet - Page 3

• Manufacturer Part Number: EVAL-AD7654CBZ
• Description: BOARD EVALUATION FOR AD7654
• Manufacturer: Analog Devices Inc
• Series: PulSAR®r

Specifications of EVAL-AD7654CBZ

• Number Of Adc's: 2
• Number Of Bits: 16
• Sampling Rate (per Second): 500k
• Data Interface: Serial, Parallel
• Inputs Per Adc: 2 Differential
• Input Range: 0 ~ 5 V
• Power (typ) @ Conditions: 120mW @ 500kSPS
• Voltage Supply Source: Analog and Digital
• Operating Temperature: -40°C ~ 85°C
• Utilized Ic / Part: AD7654
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Preliminary Technical Data
OVERVIEW
Figure 1 shows the EVAL-AD76XXCBZ evaluation board.
When used in stand-alone mode or in conjunction with the
CED/ECB, the gate array, U10, provides the necessary control
signals for conversion and buffers the ADC data. The evaluation
board is a flexible design that enables the user to choose among
many different board configurations, analog signal
conditioning, reference, and different modes of conversion data.
CONVERSION CONTROL/MASTER CLOCK
Conversion start ( CNVST ) controls the sample rate of the ADC
and is the only input needed for conversion; all SAR timing is
generated internally. CNVST is generated either by the gate
array or externally via J3 (SMB) and setting JP22 in the external
(EXT) position. The evaluation board is factory configured for
the CNVST range shown in Table 1. Externally generated
CNVST should have very low jitter and sharp edges for the
maximum dynamic performance of the part. Since CNVST
jitter usually results in poor SNR performance, it is
recommended to use the on-board CNVST generation
whenever possible.
The master clock (MCLK) source for the gate array is generated
from the CED/ECB capture board or from U12, the 40MHz
local oscillator selectable when using the accompanying
software. The range for CNVST in Table 1is a ratio generated
from this master clock. In stand-alone mode, other clock
frequencies can be used to change the gate array generated
CNVST by this ratio. However, other timings will be affected –
namely the slave serial clock (SCLK) interface. In serial slave
mode, SCLK = MCLK.
While the ADC is converting, activity on the BUSY pin turns on
the LED, D2. Additionally, the BUSY signal can be monitored
test point TP1. Buffered conversion data (BD) is available at
U10 on the output bus BD[0:15] on the 40-pin IDC connector
P2, and on the 96-pin connector P3. When operating with the
ECB/CED, data is transferred using a 16 bit bus and
corresponding word and byte modes selectable with the
software. For the 18 bit converters two consecutive 16 bit words
are read, however, the ADC data is still read into the gate array
as 18 bits. Additionally, BD is updated on the falling edge of
BBUSY on P3-C17, and on the rising edge of DBUSY on P2-33.
When either parallel or serial reading mode of the ADC is used,
data is available on this parallel bus.
When using Serial Mode, serial data is available at T3, T4, T5,
and T6 (SDOUT, SCLK, SYNC and RDERROR) and buffered
serial data is output on TP17, TP18, and TP19 (SCLK, SYNC,
and SDOUT). When using Slave Serial Mode, the external serial
clock SCLK applied to the ADC is the MCLK, U12, frequency
(40MHz). Refer to the device specific datasheet for full details
of the interface modes.
Rev. PrA | Page 3 of 30
The analog input amplifier circuitry (U6, U7 and discretes)
allows configuration changes such as positive or negative gain,
input range scaling, filtering, addition of a DC component, use
of different op-amp and supplies depending on the ADC. The
analog input amplifiers are set as unity gain buffers at the
factory. The supplies are selectable with solder pads and are set
for the ±12V range. Table 1 shows the analog input range for the
available evaluation boards.
The default configuration for the single ended (SE) unipolar
ADCs sets U6 at mid-scale from the voltage divider (V
R6/(R6+R7)) and U7 at mid-scale from the voltage divider (V
* R29(R29+R60)) for the differential unipolar ADCs.
For the bipolar devices, the input is at 0V (mid-scale). This
allows a transition noise test (histogram) without any other
equipment. In some applications, it is desired to use a bipolar or
wider analog input range, for instance, ± 10V, ± 5V, ± 2.5V, or 0
to -5V. For the AD76XX-48 parts which do not use these input
ranges directly, simple modifications of the input driver
circuitry can be made without any performance degradation.
Refer to the datasheet under the Application Hints section for
component values or to application note AN594 on the product
web page for other input ranges.
For dynamic performance, an FFT test can be done by applying
a very low distortion AC source.
POWER SUPPLIES AND GROUNDING
The evaluation board ground plane is separated into two
sections: a plane for the digital interface circuitry and an analog
plane for the analog input and external reference circuitry. To
attain high resolution performance, the board was designed to
ensure that all digital ground return paths do not cross the
analog ground return paths by connecting the planes together
directly under the converter. Power is supplied to the board
through P3 when using with the EVAL-CONTROL-BRDX
USING THE EVAL-AD762X/AD765X/AD766X/
AD767XCBZ AS STAND-ALONE
Using the evaluation board as stand-alone does not require the
CED/ECB nor does it require use of the accompanied software.
When the CONTROL input to the gate array is LOW, which is
pulled down by default, the gate array provides the necessary
signals for conversion and buffers the conversion data.
In stand-alone mode, the gate arrays flexible logic buffers the
ADC data according to the read data mode configuration (word
or byte). In parallel reading mode the board is configured for
continuous reading since CS and RD are always driven LOW by
the gate array. Thus, the digital bus is not tri-stated in this mode
of operation and BD[0:15] will continuously be updated after a
new conversion. BD[0:15] is available on P2 after BUSY goes
HIGH. Note that with the 18 bit devices the full 18 bits of data
BD[-2:15] are output directly on P2 since the evaluation board
ANALOG INPUT
EVAL-AD76XXCBZ
CM
*
CM