DS26334DK Maxim Integrated Products, DS26334DK Datasheet - Page 13

• Manufacturer Part Number: DS26334DK
• Description: KIT DESIGN FOR DS26334
• Manufacturer: Maxim Integrated Products

Specifications of DS26334DK

• Main Purpose: Telecom, Line Interface Units (LIUs)
• Utilized Ic / Part: DS26334
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Secondary Attributes: -
• Embedded: -
• Primary Attributes: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

ID REGISTERS
BID: BOARD ID (Offset = 0X0000)
XBIDH: HIGH NIBBLE EXTENDED BOARD ID (Offset = 0X0002)
XBIDM: MIDDLE NIBBLE EXTENDED BOARD ID (Offset = 0X0003)
XBIDL: LOW NIBBLE EXTENDED BOARD ID (Offset = 0X0004)
BREV: BOARD FAB REVISION (Offset = 0X0005)
AREV: BOARD ASSEMBLY REVISION (Offset = 0X0006)
PREV: FPGA REVISION (Offset = 0X0007)
CONTROL REGISTERS
Register Name: CTRL_1
Register Description: DS26334DK FPGA CONTROL REGISTER 1
Register Offset: 0x08
Bit #
Name
Bit 7: ENRLOS16. This bit enables the RLOS16 LED. This should not be enabled when driving TECLK from the
DS26334/DS26324.
Bit 6: ENRLOS15. This bit enables the RLOS15 LED. This should not be enabled when driving CLKA from the
DS26334/DS26324.
Bit 5: CLKE. This bit sets the CLKE pin on the DS26334/DS26324. This is only active when SPI (Bit 0) is HIGH. If
SPI (Bit 0) is low, CLKE is always low.
Bit 4: SPI_SWAP. This bit sets the BSWP/A5 pin on the DS26334/DS26324. This is only active when SPI (Bit 0) is
HIGH.
Bit 3: SPI. This bit sets up the FPGA to use serial mode. This bit also changes the mode pin on the
DS26334/DS26324.
Bit 2: OE. This bit controls the OE pin to the DS26334.
Bits 1 and 0: MCLK1 and MCLK0. These bits control the MCLK pin to the DS26334/DS26324.
BID is read-only with a value of 0xD.
XBIDH is read-only with a value of 0x0.
XBIDM is read-only with a value of 0x1.
XBIDL is read-only with a value of 0x6.
BREV is read-only and displays the current fab revision.
AREV is read-only and displays the current assembly revision.
PREV is read-only and displays the current PLD firmware revision.
If ENRLOS16 = LOW, the RLOS16 LED is not enabled.
If ENRLOS16 = HIGH, the RLOS16 LED is enabled and lights when RLOS16 is high.
If ENRLOS15 = LOW, the RLOS15 LED is not enabled.
If ENRLOS15 = HIGH, the RLOS15 LED is enabled and lights when RLOS15 is high.
If CLKE = LOW, SDO is clocked out on the rising edge of SCLK.
If CLKE = HIGH, SDO is clocked out on the falling edge of SCLK.
If SPI_SWAP = LOW, the SPI bus is LSB first.
If SPI_SWAP = HIGH, the SPI bus is MSB first.
If SPI = LOW, the parallel bus is used for all read/write access. This also sets the MODE pin on the
If SPI = HIGH, the SPI bus is used for all read/write access. This also sets the MODE pin on the
MCLK1
DS26334/DS26324 to logic 1.
DS26334/DS26324 to logic 0.
0
0
1
1
ENRLOS16
7
MCLK0
0
1
0
1
ENRLOS15
6
MCLK = high-impedance mode
MCLK = on-board T1 oscillator
MCLK = on-board E1 oscillator
MCLK = user clock input
DESCRIPTION OF MCLK
CLKE
5
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SPI_SWAP
4
SPI
3
OE
2
MCLK1
1
MCLK0
0