SI5319-EVB Silicon Laboratories Inc, SI5319-EVB Datasheet - Page 9

• Manufacturer Part Number: SI5319-EVB
• Description: BOARD EVALUATION SI5319
• Manufacturer: Silicon Laboratories Inc

Specifications of SI5319-EVB

• Main Purpose: Timing, Clock Multiplier
• Embedded: No
• Utilized Ic / Part: SI5319
• Primary Attributes: 1 Input, 1 Output
• Secondary Attributes: CML, CMOS, LVDS, LVPECL
• Processor To Be Evaluated: Si5319
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant, Lead free / RoHS Compliant

J14 is a 10 pin ribbon header that provides an external path to monitor the status pins.
J17 is a 10 pin ribbon header that provides an external path to serially communicate with the Any-Rate Precision
Clock.
To control the Any-Rate part that is on the Evaluation Board from an external serial port, open the Register
Programmer, connect to the Evaluation Board, go to Options in the top toolbar, and select "Switch To External
Control Mode."
To control an Any-Rate part that is on an external target board from the Evaluation Board using its serial port, tie
pin 9 of J17 low so that the on-board Any-Rate part is constantly being held in reset. This will force it to disable its
SDA_SDO output buffer. This will work only for Evaluation Boards that have Rev C or higher Any-Rate parts.
J9 is a three-pin by twenty header that is used to establish input levels for the pin controlled two and three-level
inputs using jumper plugs. It also provides a means of externally driving the two and three-level input signals.
J12 is used to monitor the Any-Rate Precision Clock voltage.
J1 and J2 are edge mount SMA connectors that are used, if so configured, to supply an external single-ended or
differential 38.88 MHz reference oscillator.
J9.10B
J9.1B
J9.2B
J9.3B
J9.4B
J9.5B
J9.6B
J9.7B
J9.8B
J9.9B
J9
Table 6. Two and Three Level Input Jumper Headers, J9
SCL_SCLK_BWSEL0
SDA_SDO_BWSEL1
A2_SS_FRQSEL2
SDI_FRQSEL3
A0_FRQSEL0
A1_FRQSEL1
AUTOSEL
Table 5. External Serial Port Connector, J17
FRQTBL
CMODE
CS_CA
Pin
J17.1
J17.3
J17.5
J17.7
J17.9
J14.1
J14.3
J14.5
J14.7
J14.9
J17
J14
Table 4. Status Header, J14
DUT_RST_B
SCL_SCLK
DUT_PWR
SDA_SDO
CS_CA
A2_SS
Rev. 0.4
C1B
C2B
LOL
SDI
Pin
Pin
J9.12B
J9.11B
J9.13B
J9.14B
J9.15B
J9.16B
J9.17B
J9.18B
J9.19B
J9.20B
J9
clock active
Comment
Comment
not reset
DBL2_BY
SFOUT0
SFOUT1
RATE0
RATE1
DEC
INC
Pin
—
—
—
Si531x-EVB
Si532x-EVB
Comment
not used
not used
not used
9