SI5322/23-EVB Silicon Laboratories Inc, SI5322/23-EVB Datasheet - Page 8

• Manufacturer Part Number: SI5322/23-EVB
• Description: BOARD EVAL FOR SI5322/23
• Manufacturer: Silicon Laboratories Inc

Specifications of SI5322/23-EVB

• Main Purpose: Timing, Clock Generator
• Utilized Ic / Part: SI5322, SI5323
• Processor To Be Evaluated: Si5322 and Si5323
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Secondary Attributes: -
• Embedded: -
• Primary Attributes: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

Si5322
8
5, 10, 11,
6, 8,19,
15, 32
20, 31
Pin #
12
13
14
16
17
4
9
AUTOSEL
Pin Name
DBL2_BY
CKIN2+
CKIN2–
CKIN1+
CKIN1–
GND
C2B
V
DD
Table 3. Si5322 Pin Descriptions (Continued)
GND
V
I/O
O
DD
I
I
I
I
Signal Level
LVCMOS
3-Level
3-Level
Supply
Supply
Multi
Multi
Preliminary Rev. 0.5
CKIN2 Loss of Signal.
Active high loss-of-signal indicator for CKIN2. Once trig-
gered, the alarm will remain active until CKIN2 is validated.
0 = CKIN2 present.
1 = LOS on CKIN2.
Supply.
The device operates from a 1.8, 2.5, or 3.3 V supply. Bypass
capacitors should be associated with the following V
5
10
32
A 1.0 µF should be placed as close to device as is practical.
Ground.
Must be connected to system ground. Minimize the ground
path impedance for optimal performance of this device.
Manual/Automatic Clock Selection.
Three level input that selects the method of input clock
selection to be used.
L = Manual.
M = Automatic non-revertive.
H = Automatic revertive.
The pin has a weak pull-up and weak pull-down and
defaults to M.
Some designs may require an external resistor voltage
divider when driven by an active device that will tri-state.
Clock Input 2.
Differential input clock. This input can also be driven with a
single-ended signal. Input frequency selected from a table
of values. The same frequency must be applied to CKIN1
and CKIN2.
Output 2 Disable/Bypass Mode Control.
Controls enable of CKOUT2 divider/output buffer path and
PLL bypass mode.
L = CKOUT2 enabled.
M = CKOUT2 disabled.
H = Bypass mode with CKOUT2 enabled.
The pin has a weak pull-up and weak pull-down and
defaults to M.
Some designs may require an external resistor voltage
divider when driven by an active device that will tri-state.
Clock Input 1.
Differential input clock. This input can also be driven with a
single-ended signal. Input frequency selected from a table
of values. The same frequency must be applied to CKIN1
and CKIN2.
0.1 µF
0.1 µF
0.1 µF
Description
DD
pins: