SI5322/23-EVB Silicon Laboratories Inc, SI5322/23-EVB Datasheet
SI5322/23-EVB
Specifications of SI5322/23-EVB
Related parts for SI5322/23-EVB
SI5322/23-EVB Summary of contents
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ROGRAMMABLE Description The Si5322 is a low jitter, precision clock multiplier for high-speed communication systems, including SONET OC-48/OC-192, Ethernet, and Fibre Channel. The Si5322 accepts dual clock inputs ranging from 19.44 to 707 MHz and ...
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Si5322 Table 1. Performance Specifications (V = 1.8 ±5%, 2.5 ±10%, or 3.3 V ±10 Parameter Symbol Temperature Range T A Supply Voltage V DD Supply Current I DD Input Clock Frequency CK F (CKIN1, CKIN2) Output Clock ...
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Table 1. Performance Specifications (V = 1.8 ±5%, 2.5 ±10%, or 3.3 V ±10 Parameter Symbol Duty Cycle Uncertainty CKO DC PLL Performance Jitter Generation J GEN Jitter Transfer J PK Phase Noise CKO PN Subharmonic Noise SP ...
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Si5322 622 MHz In, 622 MHz Out BW=877 kHz -50 -70 -90 -110 -130 -150 -170 1000 10000 OC-48, 12 kHz to 20 MHz OC-192, 20 kHz to 80 MHz OC-192, 4 MHz to 80 MHz OC-192, 50 kHz to ...
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System Power Supply 130 Ω 130 Ω CKIN1+ CKIN1– 82 Ω 82 Ω Input Clock Sources 130 Ω 130 Ω CKIN2+ CKIN2– 82 Ω 82 Ω Manual/Automatic Clock AUTOSEL ...
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Si5322 1. Functional Description The Si5322 is a low jitter, precision clock multiplier for high-speed communication systems, including SONET OC-48/OC-192, SDH STM-16/64 Ethernet, and Fibre Channel. The Si5322 accepts dual clock inputs ranging from 19.44 to 707 MHz and generates ...
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Pin Descriptions: Si5322 FRQTBL AUTOSEL Pin assignments are preliminary and subject to change. Pin # Pin Name I/O 1 RST I 2 FRQTBL I 3 C1B RST 1 27 ...
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Si5322 Table 3. Si5322 Pin Descriptions (Continued) Pin # Pin Name I/O 4 C2B O 5, 10 8,19, GND GND 20 AUTOSEL I 12 CKIN2 CKIN2– 14 DBL2_BY ...
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Table 3. Si5322 Pin Descriptions (Continued) Pin # Pin Name I/O Signal Level 21 CS_CA I/O 23 BWSEL1 I 22 BWSEL0 27 FRQSEL3 26 FRQSEL2 I 25 FRQSEL1 24 FRQSEL0 Input Clock Select/Active Clock Indicator. Input: If manual clock selection ...
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Si5322 Table 3. Si5322 Pin Descriptions (Continued) Pin # Pin Name I/O 33 SFOUT0 I 30 SFOUT1 34 CKOUT2– CKOUT2+ 29 CKOUT1– CKOUT1 — GND PAD GND GND 10 Signal Level Signal ...
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Ordering Guide Ordering Part Number Si5322-C-GM 36-Lead QFN Package ROHS6, Pb-Free Yes Preliminary Rev. 0.5 Si5322 Temperature Range – °C 11 ...
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Si5322 4. Package Outline: 36-Pin QFN Figure 3 illustrates the package details for the Si5322. Table 4 lists the values for the dimensions shown in the illustration. Figure 3. 36-Pin Quad Flat No-lead (QFN) Symbol Millimeters Min Nom A 0.80 ...
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Recommended PCB Layout Figure 4. PCB Land Pattern Diagram Preliminary Rev. 0.5 Si5322 13 ...
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Si5322 Table 5. PCB Land Pattern Dimensions Dimension Notes (General): 1. All dimensions shown are in millimeters (mm) unless otherwise noted. 2. Dimensioning and Tolerancing is per the ANSI ...
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OCUMENT HANGE IST Revision 0.44 to Revision 0.45 Condensed format. Revision 0.45 to Revision 0.46 Removed references to latency control, INC, and DEC in figures and text. Changed LVTTL to LVCMOS in Table 2, “Absolute Maximum Ratings,” ...
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