SI5316-EVB Silicon Laboratories Inc, SI5316-EVB Datasheet - Page 10

• Manufacturer Part Number: SI5316-EVB
• Description: BOARD EVAL FOR SI5316
• Manufacturer: Silicon Laboratories Inc

Specifications of SI5316-EVB

• Main Purpose: Timing, Clock Generator
• Utilized Ic / Part: SI5316
• Processor To Be Evaluated: Si5316
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Secondary Attributes: -
• Embedded: -
• Primary Attributes: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

GND PAD
*Note: Denotes 3-Level input pin with states designated as L (ground), M (VDD/2), and H (VDD).
Si5316
10
Pin #
33
30
34
35
Pin Name
CKOUT+
SFOUT0
SFOUT1
CKOUT–
GND
GND
I/O
O
I
Table 3. Si5316 Pin Descriptions (Continued)
Signal Level
3-Level
Supply
Multi
Signal Format Select.
Three level inputs that select the output signal format (common
mode voltage and differential swing) for CKOUT. Valid settings
include LVPECL, LVDS, and CML. Also includes selections for
CMOS mode, tristate mode, and tristate/sleep mode.
These pins have both weak pull-ups and weak pull-downs and
default to M.
Some designs may require an external resistor voltage divider when
driven by an active device that will tri-state.
Clock Output.
Differential output clock with a frequency selected from a table of val-
ues. Output signal format is selected by SFOUT pins. Output is differ-
ential for LVPECL, LVDS, and CML compatible modes. For CMOS
format, both output pins drive identical single-ended clock outputs.
Ground Pad.
The ground pad must provide a low thermal and electrical impedance
to a ground plane.
Rev. 0.4
SFOUT[1:0]
MM
HM
MH
HH
ML
LM
HL
LH
LL
Description
LVDS
Reserved
CML
LVPECL
Reserved
LVDS—low swing
CMOS
Disabled
Reserved
Signal Format