SI5316-EVB Silicon Laboratories Inc, SI5316-EVB Datasheet
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SI5316-EVB
Specifications of SI5316-EVB
Related parts for SI5316-EVB
SI5316-EVB Summary of contents
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... The Si5316 is a low jitter, precision jitter attenuator for high-speed communication systems, including OC-48, OC-192, 10G Ethernet, and 10G Fibre Channel. The Si5316 accepts dual clock inputs in the 19, 38, 77, 155, 311, or 622 MHz frequency range and generates a jitter-attenuated clock output at the same frequency. ...
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... Si5316 Table 1. Performance Specifications (V = 1.8 ±5%, 2.5 ±10%, or 3.3 V ±10 Parameter Symbol Temperature Range T A Supply Voltage V DD Supply Current I DD Input/Output Clock Fre- CK quency (CKIN1, CKIN2, CKOUT) 3-Level Input Pins Input Mid Current I IMM Input Clocks (CKIN1, CKIN2) Differential Voltage Swing ...
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... MHz offset Phase Noise @ 100 kHz Offset Max spur @ > < 100 MHz) Still Air Symbol DIG T JCT T STG Rev. 0.4 Si5316 Min Typ Max Unit — 0.05 0.1 — 30 — — –65 –50 dBc/Hz — –95 –87 dBc/Hz — ...
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... Si5316 0 -20 -40 -60 -80 -100 -120 -140 -160 100 1000 Brick Wall, 100 Hz to 100 MHz SONET_OC48, 12 kHz to 20 MHz SONET_OC192_A, 20 kHz to 80 MHz SONET_OC192_B, 4 MHz to 80 MHz SONET_OC192_C, 50 kHz to 80 MHz Brick Wall, 800 MHz 4 10000 100000 1000000 Offset Frequency (Hz) Figure 1 ...
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... Bandwidth Select kΩ 15 kΩ Signal Format Select kΩ 15 kΩ Clock Output Disable/ Bypass Mode Control 15 kΩ Reset Notes: Figure 2. Si5316 Typical Application Circuit C 1 µ 0.1 µF 3 Ferrite Bead C 0.1 µ 0.1 µF 1 CKIN1+ CKOUT+ CKIN1– ...
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... MHz frequency range and generates a jitter-attenuated clock output at the same frequency. Within each of these clock ranges, the device can be tuned approximately 15% higher SONET/SDH frequencies maximum of 710 MHz in the 622 MHz range. The Si5316 is based on Silicon Laboratories' 3rd-generation technology, which provides any-rate ...
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... Active low input that performs external hardware reset of device. Resets all internal logic to a known state. Clock outputs are tristated during reset. After rising edge of RST signal, the Si5316 will perform an internal self-calibration when a valid signal is present. This pin has a weak pull-up. ...
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... Si5316 Table 3. Si5316 Pin Descriptions (Continued) Pin # Pin Name I/O Signal Level Analog 19*, GND GND Supply 20 RATE0 I 3-Level* 15 RATE1 12 CKIN2+ I Multi 13 CKIN2– 14 DBL_BY I 3-Level* 16 CKIN1+ I Multi 17 CKIN1– 18 LOL O LVCMOS LVCMOS *Note: Denotes 3-Level input pin with states designated as L (ground), M (VDD/2), and H (VDD). ...
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... Table 3. Si5316 Pin Descriptions (Continued) Pin # Pin Name I/O Signal Level 23 BWSEL1 I 3-Level 22 BWSEL0 25 FRQSEL1 I 3-Level 24 FRQSEL0 26 CK1DIV I 3-Level 27 CK2DIV I 3-Level *Note: Denotes 3-Level input pin with states designated as L (ground), M (VDD/2), and H (VDD). Description Bandwidth Select. Three level inputs that select the DSPLL closed loop bandwidth. ...
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... Si5316 Table 3. Si5316 Pin Descriptions (Continued) Pin # Pin Name I/O Signal Level 33 SFOUT0 I 3-Level 30 SFOUT1 34 CKOUT– O Multi 35 CKOUT+ GND PAD GND GND Supply *Note: Denotes 3-Level input pin with states designated as L (ground), M (VDD/2), and H (VDD). 10 Description Signal Format Select. ...
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... Ordering Guide Ordering Part Number Si5316-C-GM 36-Lead QFN Package ROHS6, Pb-Free Yes Rev. 0.4 Si5316 Temperature Range – °C 11 ...
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... Si5316 4. Package Outline: 36-Lead QFN Figure 3 illustrates the package details for the Si5316. Table 4 lists the values for the dimensions shown in the illustration. Figure 3. 36-Pin Quad Flat No-lead (QFN) Symbol Millimeters Min Nom A 0.80 0.85 A1 0.00 0.02 b 0.18 0.25 D 6.00 BSC D2 3 ...
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... Recommended PCB Layout Figure 4. PCB Land Pattern Diagram Rev. 0.4 Si5316 13 ...
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... Si5316 Table 5. PCB Land Pattern Dimensions Dimension Notes (General): 1. All dimensions shown are in millimeters (mm) unless otherwise noted. 2. Dimensioning and Tolerancing is per the ANSI Y14.5M-1994 specification. 3. This Land Pattern Design is based on IPC-SM-782 guidelines. 4. All dimensions shown are at Maximum Material Condition (MMC). Least Material Condition (LMC) is calculated based on a Fabrication Allowance of 0 ...
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... Updated Table 1 on page 2. Updated Table 2 on page 3. Updated Table 3 on page 7. Added table under Figure 1 on page 4. Updated 1. "Functional Description" on page 6. Clarified 2. "Pin Descriptions: Si5316" on page 7 including pull-up/pull-down. Revision 0.3 to Revision 0.4 Updated Table 1, “Performance Specifications page 2. Updated Table 3, “Si5316 Pin Descriptions,” on page 7. Updated Figure 2, “ ...
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... Si5316 C I ONTACT NFORMATION Silicon Laboratories Inc. 400 West Cesar Chavez Austin, TX 78701 Tel: 1+(512) 416-8500 Fax: 1+(512) 416-9669 Toll Free: 1+(877) 444-3032 Email: Clockinfo@silabs.com Internet: www.silabs.com The information in this document is believed to be accurate in all respects at the time of publication but is subject to change without notice. ...