SI5324-EVB Silicon Laboratories Inc, SI5324-EVB Datasheet - Page 44

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SI5324-EVB

Manufacturer Part Number
SI5324-EVB
Description
BOARD EVALUATION SI5324
Manufacturer
Silicon Laboratories Inc
Datasheets

Specifications of SI5324-EVB

Main Purpose
Timing, Clock Multiplier
Embedded
No
Utilized Ic / Part
SI5324
Primary Attributes
2 Inputs, 2 Outputs
Secondary Attributes
CML, CMOS, LVDS, LVPECL
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Lead Free Status / RoHS Status
Lead free / RoHS Compliant, Lead free / RoHS Compliant
Si5324
Reset value = 0000 0001
44
Register 130.
Name
7, 5:3
Type
Bit
Bit
6
2
1
0
DIGHOLDVALID
FOS2_INT
FOS1_INT
Reserved
Reserved
LOL_INT
Name
D7
R
Digital Hold Valid.
Indicates if the digital hold circuit has enough samples of a valid clock to meet dig-
ital hold specifications.
0: Indicates digital hold history registers have not been filled. The digital hold
output frequency may not meet specifications.
1: Indicates digital hold history registers have been filled. The digital hold output
frequency is valid.
Reserved.
CKIN2 Frequency Offset Status.
0: Normal operation.
1: Internal frequency offset alarm on CKIN2 input.
CKIN1 Frequency Offset Status.
0: Normal operation.
1: Internal frequency offset alarm on CKIN1 input.
PLL Loss of Lock Status.
0: PLL locked.
1: PLL unlocked.
DIGHOLDVALID
D6
R
Preliminary Rev. 0.3
D5
Reserved
D4
R
D3
Function
FOS2_INT
D2
R
FOS1_INT
D1
R
LOL_INT
D0
R

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