SI5324-EVB Silicon Laboratories Inc, SI5324-EVB Datasheet
SI5324-EVB
Specifications of SI5324-EVB
Related parts for SI5324-EVB
SI5324-EVB Summary of contents
Page 1
... MHz and generates two output clocks ranging from 2 kHz to 945 MHz and select frequencies to 1.4 GHz. The two outputs are divided down separately from a common source. The Si5324 can also use its external reference as a clock source for frequency synthesis. The device provides virtually any frequency translation combination across this operating range ...
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... Si5324 Functional Block Diagram ÷ N31 CKIN1 CKIN2 ÷ N32 Xtal/Refclock Loss of Signal/ Frequency Offset Signal Detect Loss of Lock 2 Xtal or Refclock ® DSPLL ÷ N1_HS ÷ N2 Control 2 Clock Select I C/SPI Port Device Interrupt Skew Adjust Rate Select Preliminary Rev. 0.3 ÷ NC1_LS CKOUT1 ÷ ...
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... Section 1. Electrical Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4 2. Typical Phase Noise Performance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .7 3. Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 3.1. External Reference . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 3.2. Additional Documentation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 4. Pin Descriptions: Si5324 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .13 5. Register Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 6. Register Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .19 6.1. ICAL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52 7. Ordering Guide . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53 8. Package Outline: 36-Pin QFN . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55 9. Recommended PCB Layout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56 10 ...
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... Si5324 1. Electrical Specifications Table 1. Performance Specifications (V = 1.8 ±5%, 2.5 ±10%, or 3.3 V ±10 Parameter Symbol Temperature Range T A Supply Voltage V DD Supply Current I DD Input Clock Frequency CK F (CKIN1, CKIN2) Output Clock Frequency CK OF (CKOUT1, CKOUT2) 3-Level Input Pins (RATE0 and RATE1) ...
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... MHz offset — Max spur @ — (n > < 100 MHz) Still Air — Still Air — Preliminary Rev. 0.3 Si5324 Typ Max Unit — V – 1. — 1.9 V — 0.93 V 230 350 ps — ...
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... Si5324 Table 2. Absolute Maximum Ratings Parameter DC Supply Voltage LVCMOS Input Voltage CKINn Voltage Level Limits XA/XB Voltage Level Limits Operating Junction Temperature Storage Temperature Range ESD HBM Tolerance (100 pF, 1.5 k); All pins except CKIN+/CKIN– ESD MM Tolerance; All pins except CKIN+/CKIN– ...
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... Typical Phase Noise Performance Jitter Bandwidth MHz Note: Number of samples: 8.91E9 Figure 1. Broadcast Video Jitter (peak-peak) 5.24 ps Preliminary Rev. 0.3 Si5324 Jitter (RMS) 484 7 ...
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... Si5324 Note: Phase noise plot uses brick wall integration. Jitter Bandwidth SONET_OC48, 12 kHz to 20 MHz SONET_OC192_A, 20 kHz to 80 MHz SONET_OC192_B, 4 MHz to 80 MHz SONET_OC192_C, 50 kHz to 80 MHz Brick Wall_800 MHz Note: Jitter integration bands include low-pass (–20 dB/Dec) and hi-pass (–60 dB/Dec) roll-offs per Telecordia GR-253-CORE ...
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... Figure 3. Wireless Base Station Phase Noise Jitter Bandwidth Jitter (peak-peak MHz Note: Number of samples: 8.91E9 Preliminary Rev. 0.3 Jitter (RMS) 7.28 ps 581 Si5324 9 ...
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... Input Clock Sources* 130 82 Option 1: Crystal Crystal/Ref Clk Rate Option 2: Refclk+ Refclk– Control Mode (H) Reset Figure 5. Si5324 Typical Application Circuit (SPI Control Mode µF 4 System C 0.1 µF 1 Power Ferrite Supply Bead C 0.1 µ 0.1 µF 3 130 ...
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... Si5324 accepts two input clocks ranging from 2 kHz to 710 MHz and generates two output clocks ranging from 2 kHz to 945 MHz and select frequencies to 1.4 GHz. The Si5324 can also use its external reference as a clock source for frequency synthesis. The device provides virtually any frequency translation combination across this operating range ...
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... To address this issue, a stable external reference, TXCO, OCXO, or thermally- isolated crystal is recommended. For example, with a 20 ppm oscillator as the reference on the XA/XB pins, temperature changes cause the oscillator to change frequency slightly. Although the Si5324 is locked to its input on CLKIN, it also uses the XA/ reference. 3.2. Additional Documentation Consult the Silicon Laboratories Any-Frequency Precision Clock Family Reference Manual (FRM) for detailed information about the Si5324 ...
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... Pin Descriptions: Si5324 INT_C1B Pin # Pin Name I/O Signal Level 1 I LVCMOS RST 2, 9, 14 INT_C1B O LVCMOS 4 C2B O LVCMOS Note: Internal register names are indicated by underlined italics, e.g., INT_PIN. See Si5324 Register Map RST 1 27 SDI A2_SS C2B GND VDD 5 23 ...
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... Multi 13 CKIN2– 18 LOL O LVCMOS Note: Internal register names are indicated by underlined italics, e.g., INT_PIN. See Si5324 Register Map. 14 Description Supply. The device operates from a 1.8, 2.5, or 3.3 V supply. Bypass capac- itors should be associated with the following Vdd pins: 5 0.1 µF 10 0.1 µ ...
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... LVCMOS 27 SDI I LVCMOS Note: Internal register names are indicated by underlined italics, e.g., INT_PIN. See Si5324 Register Map. Description Input Clock Select/Active Clock Indicator. Input: In manual clock selection mode, this pin functions as the manual input clock selector if the CKSEL_PIN is set Select CKIN1. ...
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... I LVCMOS GND PAD GND GND Supply Note: Internal register names are indicated by underlined italics, e.g., INT_PIN. See Si5324 Register Map. 16 Description Output Clock 1. Differential output clock with a frequency range of 8 kHz to 1.4175 GHz. Output signal format is selected by SFOUT1_REG register bits. Output is differential for LVPECL, LVDS, and CML compatible modes ...
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... DHOLD SQ_ICAL SFOUT2_REG[2:0} HLOG_1[1:0] DSBL2_ REG VALTIME[1:0] CK2_BAD_PIN CK_ACTV_ POL NC1_LS[15:8] NC1_LS[7:0] NC2_LS[15:8] NC2_LS[7:0] N2_LS[15:8] N2_LS[7:0] N31[15:8] N31[7:0] Preliminary Rev. 0.3 Si5324 D2 D1 BYPASS_REG CK_PRIOR[1:0] HST_DEL[4:0] SFOUT1_REG[2:0] FOSREFSEL[2:0] DSBL1_ REG PD_CK2 PD_CK1 LOCK[T2:0] CK1_ BAD_ PIN LOL_PIN INT_PIN CK1_ACTV_PIN CKSEL_PIN CK_BAD_ POL ...
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... Si5324 Register 128 129 130 DIGHOLD- VALID 131 132 134 135 PARTNUM_RO[3:0] 136 RST_REG ICAL 137 138 139 LOS2_EN[0:0] LOS1_EN[0:0] 142 143 185 Table 3. CKOUT_ALWAYS_ON and SQ_ICAL Truth Table CKOUT_ALWAYS_ON N32[15:8] N32[7:0] CLKIN2RATE[2:0] FOS2_FLG PARTNUM_RO[11:4] INDEPENDENTSKEW1[7:0] INDEPENDENTSKEW2[7:0] NVM_REVID[7:0] SQ_ICAL 0 CKOUT OFF until after the first ICAL ...
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... This bit enables or disables the PLL bypass mode. Use only when the device is in digital hold or before the first ICAL. Bypass mode is not supported for CMOS output clocks. 0: Normal operation 1: Bypass mode. Selected input clock is connected to CKOUT buffers, bypassing PLL. 0 Reserved Reserved Function Preliminary Rev. 0.3 Si5324 BYPASS_ REG R R ...
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... Si5324 Register 1. Bit D7 D6 Name Reserved Type R Reset value = 1110 0100 Bit Name 7:4 Reserved Reserved. 3:2 CK_PRIOR2 CK_PRIOR 2. [1:0] Selects which of the input clocks will be 2nd priority in the autoselection state machine. 00: CKIN1 is 2nd priority. 01: CKIN2 is 2nd priority. 10: Reserved 11: Reserved 1:0 CK_PRIOR1 CK_PRIOR 1 ...
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... This bit determines if the output clocks will remain enabled or be squelched (disabled) during an internal calibration. See Table 3 on page 18. 0: Output clocks enabled during ICAL. 1: Output clocks disabled during ICAL. 3:0 Reserved Reserved DHOLD SQ_ICAL R/W R/W Function Preliminary Rev. 0.3 Si5324 Reserved R . CKSEL_REG consequence 21 ...
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... Si5324 Register 4. Bit D7 D6 Name AUTOSEL_REG [1:0] Type R/W Reset value = 0001 0010 Bit Name 7:6 AUTOSEL_ AUTOSEL_REG [1:0] REG [1:0] Selects method of input clock selection to be used. 00: Manual (either register or pin controlled, see CKSEL_PIN) 01: Automatic Non-Revertive 10: Automatic Revertive 11: Reserved 5 Reserved Reserved ...
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... Controls output signal format and disable for CKOUT1 output buffer. Bypass mode is not supported for CMOS output clocks. 000: Reserved 001: Disable 010: CMOS 011: Low swing LVDS 100: Reserved 101: LVPECL 110: CML 111: LVDS SFOUT2_REG [2:0] R/W Function Preliminary Rev. 0.3 Si5324 SFOUT1_REG [2:0] R/W 23 ...
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... Si5324 Register 7. Bit D7 D6 Name Type Reset value = 0010 1010 Bit Name 7:3 Reserved. Reserved. 2:0 FOSREFSEL FOSREFSEL [2:0]. [2:0] Selects which input clock is used as the reference frequency for Frequency Off-Set (FOS) alarms. 000: XA/XB (External reference) 001: CKIN1 010: CKIN2 ...
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... HIST_AVG [4:0] Type Reset value = 1100 0000 Bit Name 7:3 HIST_AVG HIST_AVG [4:0]. [4:0] Selects amount of averaging time to be used in generating the history information for Digital Hold. 2:0 Reserved Reserved HLOG_1[1:0] R/W Function R/W Function Preliminary Rev. 0.3 Si5324 Reserved Reserved ...
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... Si5324 Register 10. Bit D7 D6 Name Reserved Type R Reset value = 0000 0000 Bit Name 7:4 Reserved Reserved. 3 DSBL2_REG DSBL2_REG. This bit controls the powerdown of the CKOUT2 output buffer. If disable mode is selected, the NC2 output divider is also powered down. 0: CKOUT2 enabled. 1: CKOUT2 disabled. ...
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... DSPLL. Refer to the Family Reference Manual for more details. To minimize lock time, the value 001 for LOCKT is recommended. 000: 106 ms 001 010: 26.5 ms 011: 13.3 ms 100: 6.6 ms 101: 3.3 ms 110: 1.66 ms 111: .833 VALTIME [1:0] R/W Function Preliminary Rev. 0.3 Si5324 LOCKT [2:0] R/W 27 ...
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... Si5324 Register 20. Bit Name Reserved Type R Reset value = 0011 1110 Bit Name 7:4 Reserved Reserved. 3 CK2_BAD_PIN CK2_BAD_PIN. The CK2_BAD status can be reflected on the C2B output pin. 0: C2B output pin tristated 1: C2B status reflected to output pin 2 CK1_BAD_PIN CK1_BAD_PIN. The CK1_BAD status can be reflected on the C1B output pin. ...
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... CKSEL_REG[1:0] register bits or the CS_CA input pin. This bit is only active when AUTOSEL_REG = Manual. 0: CS_CA pin is ignored. CKSEL_REG[1:0] register bits control clock selection. 1: CS_CA input pin controls clock selection Reserved Function Preliminary Rev. 0.3 Si5324 D1 D0 CK1_ACTV_PIN CKSEL_ PIN R/W R/W 29 ...
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... Si5324 Register 22. Bit Name Reserved Type R Reset value = 1101 1111 Bit Name 7:4 Reserved Reserved. 3 CK_ACTV_ POL CK_ACTV_POL. Sets the active polarity for the CS_CA signals when reflected on an output pin. 0: Active low 1: Active high 2 CK_BAD_ POL CK_BAD_POL. Sets the active polarity for the INT_C1B and C2B signals when reflected on output pins ...
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... Determines if a LOS on XA/XB(LOSX_FLG) is used in the generation of an interrupt. Writes to this register do not change the value held in the LOSX_FLG register. 0: LOSX alarm triggers active interrupt on INT_C1B output (if INT_PIN=1). 1: LOSX_FLG ignored in generating interrupt output LOS2_ MSK R/W Function Preliminary Rev. 0.3 Si5324 D1 D0 LOS1_ MSK LOSX_ MSK R/W R/W 31 ...
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... Si5324 Register 24. Bit D7 D6 Name Reserved Type Reset value = 0011 1111 Bit Name 7:3 Reserved Reserved. 2 FOS2_MSK FOS2_MSK. Determines if the FOS2_FLG is used to in the generation of an interrupt. Writes to this register do not change the value held in the FOS2_FLG register. 0: FOS2 alarm triggers active interrupt on INT_C1B output (if INT_PIN=1). ...
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... Bit Name 7:4 Reserved Reserved. 3:0 NC1_LS NC1_LS [19:16]. [19:16] Sets value for NC1 low-speed divider, which drives CKOUT1 output. Must odd. 00000000000000000000 = 1 00000000000000000001 = 2 00000000000000000011 = 4 00000000000000000101 = 6 ... 11111111111111111111=2^20 Valid divider values=[ ..., 2^20 Function Function Preliminary Rev. 0.3 Si5324 Reserved NC1_LS [19:16] R/W 33 ...
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... Si5324 Register 32. Bit D7 D6 Name Type Reset value = 0000 0000 Bit Name 7:0 NC1_LS NC1_LS [15:8]. [15:8] Sets value for NC1 low-speed divider, which drives CKOUT1 output. Must odd. 00000000000000000000 = 1 00000000000000000001 = 2 00000000000000000011 = 4 00000000000000000101 = 6 ... 11111111111111111111=2^20 Valid divider values=[ ..., 2^20] Register 33. Bit D7 D6 ...
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... Reset value = 0000 0000 Bit Name 7:0 NC2_LS [15:8] NC2_LS [15:8] Sets value for NC2 low-speed divider, which drives CKOUT2 output. Must odd. 00000000000000000000 = 1 00000000000000000001 = 2 00000000000000000011 = 4 00000000000000000101 = 6 ... 11111111111111111111=2^20 Valid divider values=[ ..., 2^20 Function NC2_LS [15:8] R/W Function . Preliminary Rev. 0.3 Si5324 NC2_LS [19:16] R ...
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... Si5324 Register 36. Bit D7 D6 Name Type Reset value = 0011 0001 Bit Name 7:0 NC2_LS [7:0] NC2_LS [7:0]. Sets value for NC2 low-speed divider, which drives CKOUT2 output. Must odd. 00000000000000000000 = 1 00000000000000000001 = 2 00000000000000000011 = 4 00000000000000000101 = 6 ... 11111111111111111111 = 2 Valid divider values = [ ..., NC2_LS [7:0] R/W Function ...
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... Sets value for N2 high speed divider which drives N2LS low-speed divider. 000: 4 001: 5 010: 6 011: 7 100: 8 101: 9 110: 10 111 Reserved Reserved. 3:0 N2_LS [19:16] N2_LS [19:16]. Sets value for N2 low-speed divider, which drives phase detector. 00000000000000000001 = 2 00000000000000000011 = 4 00000000000000000101 = 6 ... 11111111111111111111 = 2 Valid divider values = [ ..., Reserved R Function Preliminary Rev. 0.3 Si5324 N2_LS [19:16] R/W 37 ...
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... Si5324 Register 41. Bit D7 D6 Name Type Reset value = 0000 0000 Bit Name 7:0 N2_LS [15:8] N2_LS [15:8]. Sets value for N2 low-speed divider, which drives phase detector. 00000000000000000001 = 2 00000000000000000011 = 4 00000000000000000101 = 6 ... 11111111111111111111 = 2 Valid divider values = [ ..., 2 Register 42. Bit D7 D6 Name Type Reset value = 1111 1001 ...
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... Valid divider values = [ ..., 2 Register 44. Bit D7 D6 Name Type Reset value = 0000 0000 Bit Name 7:0 N31_[15:8] N31_[15:8]. Sets value for input divider for CKIN1. 0000000000000000000 = 1 0000000000000000001 = 2 0000000000000000010 = 3 ... 1111111111111111111 = 2 Valid divider values = [ ..., Reserved R Function N31_[15:8] R/W Function Preliminary Rev. 0.3 Si5324 N31 [18:16] R ...
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... Si5324 Register 45. Bit D7 D6 Name Type Reset value = 0000 1001 Bit Name 7:0 N31_[7:0 N31_[7:0]. Sets value for input divider for CKIN1. 0000000000000000000 = 1 0000000000000000001 = 2 0000000000000000010 = 3 ... 1111111111111111111 = 2 Valid divider values = [ ..., 2 Register 46. Bit D7 D6 Name Type Reset value = 0000 0000 Bit Name 7:3 Reserved Reserved ...
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... Valid divider values = [ ..., 2 Register 48. Bit D7 D6 Name Type Reset value = 0000 1001 Bit Name 7:0 N32_[7:0] N32_[7:0]. Sets value for input divider for CKIN1. 0000000000000000000 = 1 0000000000000000001 = 2 0000000000000000010 = 3 ... 1111111111111111111 = 2 Valid divider values = [ ..., N32_[15:8] R/W Function N32_[7:0] R/W Function Preliminary Rev. 0.3 Si5324 ...
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... Si5324 Register 55. Bit D7 D6 Name Reserved Type R Reset value = 0000 0000 Bit Name 7:6 Reserved Reserved. 5:3 CLKIN2RATE[2:0] CLKIN2RATE_[2:0]. CKINn frequency selection for FOS alarm monitoring. 000: 10–27 MHz 001: 25–54 MHz 002: 50–105 MHz 003: 95–215 MHz 004: 190–435 MHz 005: 375– ...
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... Normal operation. 1: Internal loss-of-signal alarm on CKIN1 input. 0 LOSX_INT LOSX_INT. Indicates the LOS status of the external reference on the XA/XB pins. 0: Normal operation. 1: Internal loss-of-signal alarm on XA/XB reference clock input Reserved R Function Function Preliminary Rev. 0.3 Si5324 D1 D0 CK2_ACTV_REG CK1_ACTV_REG LOS2_INT LOS1_INT LOSX_INT ...
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... Si5324 Register 130. Bit D7 Name Reserved DIGHOLDVALID Type R Reset value = 0000 0001 Bit Name 6 DIGHOLDVALID Digital Hold Valid. Indicates if the digital hold circuit has enough samples of a valid clock to meet dig- ital hold specifications. 0: Indicates digital hold history registers have not been filled. The digital hold output frequency may not meet specifications ...
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... External Reference (signal on pins XA/XB) Loss-of-Signal Flag. 0: Normal operation 1: Held version of LOSX_INT. Generates active output interrupt if output interrupt pin is enabled (INT_PIN = 1) and if not masked by LOSX_MSK bit. Flag cleared by writing 0 to this bit Reserved R Function Preliminary Rev. 0.3 Si5324 LOS2_FLG LOS1_FLG LOSX_FLG R/W R/W R/W 45 ...
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... Si5324 Register 132. Bit D7 D6 Name Reserved Type R Reset value = 0000 0010 Bit Name 7:4, 0 Reserved Reserved. 3 FOS2_FLG CLKIN_2 Frequency Offset Flag. 0: Normal operation. 1: Held version of FOS2_INT. Generates active output interrupt if output interrupt pin is enabled (INT_PIN = 1) and if not masked by FOS2_MSK bit. Flag cleared by writing 0 to this bit ...
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... Register 134. Bit D7 D6 Name Type Reset value = 0000 0001 Bit Name 7:0 PARTNUM_RO [11:0] Device 2). 0000 0001 1000: Si5324 Others Reserved Register 135. Bit D7 D6 Name PARTNUM_RO [3:0] Type R Reset value = 1010 0010 Bit Name 7:4 PARTNUM_RO [11:0] Device 2). ...
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... Si5324 Register 136. Bit D7 D6 Name RST_REG ICAL Type R/W R/W Reset value = 0000 0000 Bit Name 7 RST_REG Internal Reset (Same as Pin Reset). Note: The I2C (or SPI) port may not be accessed until 10 ms after RST_REG is asserted. 0: Normal operation. 1: Reset of all internal logic. Outputs disabled or tristated during reset. ...
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... Note: LOS1_EN is split between two registers. 00: Disable LOS monitoring. 01: Reserved. 10: Enable LOSA monitoring. 11: Enable LOS monitoring. LOSA is a slower and less sensitive version of LOS. See the Family Reference Manual for details Reserved R Function Reserved R Function Preliminary Rev. 0.3 Si5324 FASTLOCK R LOS2_EN [1:1] LOS1_EN [1:1] R/W R/W 49 ...
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... Si5324 Register 139. Bit Name Reserved LOS2_EN [0:0] Type R R/W Reset value = 1111 1111 Bit Name 7:6, Reserved Reserved. 3:2 5 LOS2_EN [1:0] Enable CKIN2 LOS Monitoring on the Specified Input (2 of 2). Note: LOS2_EN is split between two registers. 00: Disable LOS monitoring. 01: Reserved. 10: Enable LOSA monitoring. ...
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... Default = INDEPENDENTSKEW2 [7:0] R/W Function 8 bit field that represents a twos complement of the phase offset in terms of clocks from the high speed output divider. Default = NVM_REVID [7:0] R Function Preliminary Rev. 0.3 Si5324 ...
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... Si5324 6.1. ICAL The device's registers must be configured for the intended applications. After the part is configured, the part must perform a calibration procedure when there is a stable clock on the selected CLKINn input. The calibration process is triggered by writing a "1" to bit D6 in register 136. See the Family Reference Manual for details. In addition, after a successful calibration operation, changing any of the Registers indicated in Table 4 requires that a calibration be performed again by the same procedure (writing a " ...
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... MHz Note: Add the end of the device to denote tape and reel options. Package ROHS6, Pb-Free 36-Lead QFN 36-Lead QFN 36-Lead QFN 36-Lead QFN Preliminary Rev. 0.3 Si5324 Temperature Range Yes – °C Yes – °C Yes – °C Yes – °C ...
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... Si5368 4 5 Any-Frequency Precision Clock Jitter Attenuation (Low Bandwidth 525 Hz) Si5324 2 2 Notes: 1. Maximum input and output rates may be limited by speed rating of device. See each device’s data sheet for ordering information. 2. Requires external low-cost, fixed frequency fundamental mode 40 MHz crystal or reference clock. ...
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... Package Outline: 36-Pin QFN Figure 7 illustrates the package details for the Si5324. Table 6 lists the values for the dimensions shown in the illustration. Figure 7. 36-Pin Quad Flat No-lead (QFN) Symbol Millimeters Min Nom A 0.80 A1 0.00 b 0.18 D 6.00 BSC D2 3.95 e 0.50 BSC E 6.00 BSC E2 3 ...
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... Si5324 9. Recommended PCB Layout Figure 9. Ground Pad Recommended Layout 56 Figure 8. PCB Land Pattern Diagram Preliminary Rev. 0.3 ...
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... The recommended card reflow profile is per the JEDEC/IPC J-STD-020 specification for Small Body Components. Preliminary Rev. 0.3 MIN MAX 0.50 BSC. 5.42 REF. 5.42 REF. 4.00 4.20 4.00 4.20 4.53 — 4.53 — — 0.28 0.89 REF. — 6.31 — 6.31 Si5324 57 ...
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... Si5324 10. Si5324 Device Top Mark Mark Method: Laser Font Size: 0.80 mm Right-Justified Line 1 Marking: Si5324Q Line 2 Marking: C-GM Line 3 Marking: YYWWRF Line 4 Marking: Pin 1 Identifier XXXX 58 Customer Part Number Q = Speed Code See Ordering Guide for options Product Revision G = Temperature Range – °C (RoHS6) ...
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... Si5324 OCUMENT HANGE IST Revision 0.1 to Revision 0.2 Updated Rise/Fall Time values. Updated minimum loop BW value. Revision 0.2 to Revision 0.25 Updated features and applications. Changed maximum loop bandwidth to 525 Hz (global). Updated PLL performance specifications in Table 1. ...
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... Si5324 C I ONTACT NFORMATION Silicon Laboratories Inc. 400 West Cesar Chavez Austin, TX 78701 Tel: 1+(512) 416-8500 Fax: 1+(512) 416-9669 Toll Free: 1+(877) 444-3032 Please visit the Silicon Labs Technical Support web page: https://www.silabs.com/support/pages/contacttechnicalsupport.aspx and register to submit a technical support request. The information in this document is believed to be accurate in all respects at the time of publication but is subject to change without notice. ...