LMX2433EVAL National Semiconductor, LMX2433EVAL Datasheet - Page 31

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LMX2433EVAL

Manufacturer Part Number
LMX2433EVAL
Description
EVALUATION BOARD FOR LMX2433
Manufacturer
National Semiconductor
Series
PLLatinum™r
Datasheets

Specifications of LMX2433EVAL

Main Purpose
Timing, Frequency Synthesizer
Embedded
No
Utilized Ic / Part
LMX2433
Primary Attributes
Dual Fractional-N PLL
Secondary Attributes
3.6GHz, CodeLoader Graphical User Interface
Lead Free Status / RoHS Status
Not applicable / Not applicable
Other names
*LMX2433EVAL
LMX243x OSCin Sensitivity Test Setup
The block diagram above illustrates the setup required to
measure the LMX243x device’s OSCin buffer sensitivity
level. The same setup is used for the LMX2430TM Evalua-
tion Board. This setup is similar to the FinRF sensitivity setup
except that the signal generator is now connected to the
OSCin pin and both Fin pins are tied to Vcc. The 51Ω shunt
resistor matches the OSCin input to the signal generator.
The R counter is typically set to 1000, i.e. RF_R word = 1000
or IF_R word = 1000. The reference divider output is routed
to the Ftest/LD pin by selecting the RF_R/ 2 Frequency word
(MUX[3:0] word = 14) or the IF_R/ 2 Frequency word
(MUX[3:0] word = 12) in CodeLoader. A Universal Counter is
connected to the Ftest/LD pin and is used to monitor the
31
output frequency of the reference divider. The expected
frequency should be the signal generator frequency divided
by twice the corresponding counter value, i.e. 2000. The
factor of two comes in because the LMX243x device has an
internal /2 circuit which is used to provide a 50% duty cycle.
In a similar way, sensitivity is typically measured over fre-
quency, supply voltage and temperature. In order to perform
the measurement, the temperature, frequency, and supply
voltage is set to a fixed value and the power level (voltage
level) of the signal at OSCin is varied. Sensitivity is reached
when the frequency error of the divided input signal is
greater than or equal to 1 Hz.
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