SI3215MPPQX-EVB Silicon Laboratories Inc, SI3215MPPQX-EVB Datasheet - Page 46

• Manufacturer Part Number: SI3215MPPQX-EVB
• Description: BOARD EVAL W/DISCRETE INTERFACE
• Manufacturer: Silicon Laboratories Inc
• Series: ProSLIC®r

Specifications of SI3215MPPQX-EVB

• Main Purpose: Interface, Analog Front End (AFE)
• Utilized Ic / Part: Si3215
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Secondary Attributes: -
• Embedded: -
• Primary Attributes: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

Si3215
2.11. PCM Interface
The ProSLIC contains a flexible programmable interface
for the transmission and reception of digital PCM
samples. PCM data transfer is controlled via the PCLK
and FSYNC inputs as well as the PCM Mode Select
(direct Register 1), PCM Transmit Start Count (direct
registers 2 and 3), and PCM Receive Start Count (direct
registers 4 and 5) registers. The interface can be
configured to support from 4 to 128 8-bit timeslots in
each frame. This corresponds to PCLK frequencies of
256 kHz to 8.192 MHz in power-of-2 increments.
(768 kHz and 1.536 MHz are also available.) Timeslots
for data transmission and reception are independently
configured using the TXS and RXS registers. By setting
the correct starting point of the data, the ProSLIC can
be configured to support long FSYNC and short FSYNC
variants as well as IDL2 8-bit, 10-bit, B1 and B2 channel
time slots. DTX data is high-impedance except for the
duration of the 8-bit PCM transmit. DTX will return to
46
PCLK_CNT
PCLK_CNT
FSYNC
FSYNC
PCLK
DRX
DTX
PCLK
DRX
DTX
HI-Z
Figure 27. Example, Timeslot 1, Short FSYNC (TXS/RXS = 1)
Figure 28. Example, Timeslot 1, Long FSYNC (TXS/RXS = 0)
HI-Z
0
0
MSB
MSB
1
1
MSB
MSB
2
2
3
3
4
4
5
5
Rev. 0.92
6
6
7
7
high impedance either on the negative edge of PCLK
during the LSB or on the positive edge of PCLK
following the LSB. This is based on the setting of the
TRI bit of the PCM Mode Select register. Tristating on
the negative edge allows the transmission of data by
multiple sources in adjacent timeslots without the risk of
driver contention. In addition to 8-bit data modes, there
is a 16-bit mode provided. This mode can be activated
via the PCMT bit of the PCM Mode Select register. GCI
timing is also supported in which the duration of a data
bit is two PCLK cycles. This mode is also activated via
the PCM Mode Select register. Setting the TXS or RXS
register greater than the number of PCLK cycles in a
sample period will stop data transmission because TXS
or RXS will never equal the PCLK count. Figures 27–30
illustrate the usage of the PCM highway interface to
adapt to common PCM standards.
LSB
LSB
8
8
LSB
LSB
9
9
10
10
11
11
12
12
HI-Z
HI-Z
13
13
14
14
15
15
16
16
17
17
18
18